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ꢃ ꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂ ꢍ ꢂꢋ ꢌꢎ ꢏꢀꢐꢑꢈ ꢒꢎ ꢂ ꢂ ꢐꢌ ꢉ ꢏꢋ ꢑꢓ
ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
D
Internal Voltage References . . . 50 PPM/°C
features
and 5% Accuracy
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
Glueless DSP Interface
Parallel µC/DSP Interface
Integrated FIFO
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Available in TSSOP Package
applications
D
D
D
D
D
Enhanced Product Change Notification
D
Radar Applications
†
Qualification Pedigree
D
D
D
D
Communications
High-Speed 6 MSPS ADC
Control Applications
4 Single-Ended or 2 Differential Inputs
High-Speed DSP Front-End
Selected Military Applications
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
DA PACKAGE
(TOP VIEW)
D
D
D
Differential Nonlinearity Error: 1 LSB
Integral Nonlinearity Error: 1.8 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
D0
D1
D2
D3
D4
D5
AINP
1
32
31
30
29
28
27
26
25
24
23
22
AINM
2
at f = 2 MHz
I
BINP
3
D
D
D
D
Auto-Scan Mode for 2, 3, or 4 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
BINM
4
REFIN
REFOUT
REFP
REFM
AGND
5
6
5-V Analog Single Supply Operation
BV
7
DD
†
BGND
D6
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
8
9
D7
AV
10
11
12
13
14
15
16
DD
D8
CS0
D9
21 CS1
D10/RA0
D11/RA1
20 WR (R/W)
19 RD
18
17
CONV_CLK (CONVST)
DATA_AV
DV
DD
DGND
description
The THS1206 is a CMOS, low-power, 12-bit,
6 MSPS analog-to-digital converter (ADC). The
speed, resolution, bandwidth, and single-supply
operation are suited for applications in radar,
imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error
correction logic provides for no missing codes over the full operating temperature range. Internal control
registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs,
which are sampled simultaneously. These inputs can be selected individually and configured to single-ended
or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off
of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002 − 2003, Texas Instruments Incorporated
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1
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