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TDA9917HW/25/C1 PDF预览

TDA9917HW/25/C1

更新时间: 2024-11-21 20:08:23
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
20页 120K
描述
IC 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP48, 7 X 7 MM, 1.00 MM HEIGHT, PLASTIC, MS-026, SOT545-2, QFP-48, Analog to Digital Converter

TDA9917HW/25/C1 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HTFQFP, TQFP48,.35SQ针数:48
Reach Compliance Code:compliantECCN代码:3A991.C.1
HTS代码:8542.39.00.01风险等级:5.84
最大模拟输入电压:1.45 V最小模拟输入电压:0.45 V
转换器类型:ADC, RESISTANCE LADDERJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
模拟输入通道数量:1位数:8
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, 8 BITS
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装等效代码:TQFP48,.35SQ封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH电源:1.8,3.3 V
认证状态:Not Qualified采样速率:250 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmBase Number Matches:1

TDA9917HW/25/C1 数据手册

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TDA9917  
8-bit, up to 250 Msample/s Analog-to-Digital Converter (ADC)  
Rev. 01 — 9 June 2006  
Objective data sheet  
1. General description  
The TDA9917 is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC)  
optimized for telecommunication transmission control systems and tape drive  
applications.  
The TDA9917 offers the selection between Low-Voltage Differential Signals (LVDS) and  
1.8 V Complementary Metal Oxide Semiconductor (CMOS) levels interface for the clock.  
The output data interface is 1.8 V CMOS levels. It allows to sample the signal up to  
250 Msample/s. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and  
DEL1) are 1.8 V CMOS compatible. The TDA9917 offers the most possible flexible  
acquisition control system thanks to its programmable Complete Conversion Signal (CCS)  
that allows to adjust the delay of the acquisition clock and its frequency.  
The TDA9917 is released in HTQFP48 package.  
2. Features  
I 8-bit resolution  
I High-speed sampling rate up to 250 Msample/s  
I Maximum analog input frequency up to 450 MHz  
I Programmable acquisition output clock (complete conversion signal)  
I Differential analog input  
I Integrated voltage regulator or external control for analog input full-scale  
I Integrated voltage regulator for input common-mode reference  
I Selectable 1.8 V CMOS or LVDS clock input  
I 1.8 V CMOS digital outputs  
I 1.8 V CMOS compatible static digital inputs  
I Binary or two’s complement CMOS outputs  
I Only 2 clock cycles latency  
I Industrial temperature range from 40 °C to +85 °C  
I HTQFP48 package  
3. Applications  
I 2.5G and 3G cellular base infrastructure radio transceivers  
I Wireless access systems  
I Fixed telecommunication  
I Optical networking  
I Wireless Local Area Network (WLAN) infrastructure  

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