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TDA9950TT/C2,518 PDF预览

TDA9950TT/C2,518

更新时间: 2024-11-25 21:16:31
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管商用集成电路
页数 文件大小 规格书
22页 100K
描述
IC SPECIALTY CONSUMER CIRCUIT, PDSO20, 4.40 MM, PLASTIC, SOT360-1, MO-153, TSSOP-20, Consumer IC:Other

TDA9950TT/C2,518 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDSO-G20长度:6.5 mm
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

TDA9950TT/C2,518 数据手册

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TDA9950  
CEC/I2C-bus translator  
Rev. 02 — 22 October 2009  
Product data sheet  
1. General description  
The TDA9950 is a single-chip CEC/I2C-bus translator with a processor, dedicated to the  
control and interfacing of the Consumer Electronics Control (CEC), a feature of the  
High-Definition Multimedia Interface (HDMI).  
The TDA9950 is an interface between the CEC protocol and timings and the standard  
I2C-bus. A message received on the I2C-bus interface is written in a buffer and sent on the  
CEC line. A message received from the CEC line is stored in a buffer, and an interrupt is  
generated indicating that a message can be read via the I2C-bus. To reduce its power  
consumption the TDA9950 sets itself to Idle mode when there is no message on the CEC  
line nor on the I2C-bus.  
2. Features  
2.1 Principal features  
I Receive and transmit CEC messages with compliant Signal Free Time handling  
I I2C-bus interface to host supporting 100 kbit/s and 400 kbit/s communication  
I Supports multiple CEC logical addresses  
I Supports CEC messages up to 16 bytes in length  
I Programmable retry count  
I Comprehensive arbitration and collision handling  
I 3.0 V to 3.6 V VDD operating range  
I Automatic Idle mode to reduce power consumption when there is no message on CEC  
line and I2C-bus  
I I/O pins are 5 V tolerant  
2.2 Additional features  
I Processor with embedded software to control the interface between CEC line and  
I2C-bus  
I Active-LOW reset input and on-chip power-on reset allows operation without external  
reset components. A reset counter and reset glitch suppression circuitry prevent  
spurious and incomplete resets.  
I On-chip oscillator for 12 MHz crystal  
I Schmitt trigger port inputs  
 
 
 
 

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