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TDA9955HL/17/C1:55 PDF预览

TDA9955HL/17/C1:55

更新时间: 2024-01-30 15:00:57
品牌 Logo 应用领域
恩智浦 - NXP 商用集成电路
页数 文件大小 规格书
52页 225K
描述
SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100

TDA9955HL/17/C1:55 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:100Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.65
其他特性:IT ALSO REQUIRES 3.15V TO 3.45V SUPPLY商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):1.85 V最小供电电压 (Vsup):1.75 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

TDA9955HL/17/C1:55 数据手册

 浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第2页浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第3页浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第4页浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第5页浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第6页浏览型号TDA9955HL/17/C1:55的Datasheet PDF文件第7页 
TDA9955HL  
Triple 8-bit analog-to-digital video converter for HDTV  
Rev. 01 — 17 March 2008  
Product data sheet  
1. General description  
The TDA9955HL is a triple 8-bit video converter interface.  
The TDA9955HL converts an RGB analog signal into a RGB or YUV (YCBCR) digital  
signal or converts a YUV (YPBPR) analog signal into a YUV (YCBCR) or RGB digital signal  
with a sampling rate up to 170 MHz.  
The TDA9955HL supports analog TV resolutions from 480i (720 × 480i at 60 Hz) to  
High-Definition TV (HDTV) (up to 1920 × 1080p at 60 Hz) and analog PC resolutions from  
VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz).  
The YUV digital output signal can be 4 : 4 : 4 or 4 : 2 : 2 ITU-R BT.656 standard or  
semi-planar format following the ITU-R BT.601 standard.  
All settings are controlled via the I2C-bus.  
2. Features  
I Triple 8-bit Analog-to-Digital Converter (ADC)  
I Three independent analog video sources, up to 170 MHz selectable via the I2C-bus  
I Analog composite sync slicer and recognition integrated  
I Frame and field detection for interlaced video signal  
I Video analog voltage input from 0.45 V to 0.9 V (p-p) to produce a full-scale ADC input  
of 1.0 V (p-p)  
I Three clamps for programming a 8-bit clamping code from 0 to +191 in steps of 1 LSB  
for RGB and YUV signals  
I Three video amplifiers controlled via I2C-bus to reach the full-scale resolution  
I Amplifier bandwidth of 100 MHz  
I Low gain variation with temperature  
I I2C-bus controlled Phase-Locked Loop (PLL) to generate the ADCs, formatter and  
output clocks which can be locked into a line frequency from 15 kHz to 95 kHz  
I Integrated PLL divider  
I Programmable clock phase adjustment cells  
I Matrix and offsets available for conversion of RGB or YUV signal coming from analog  
video sources into YUV or RGB  
I Output format RGB 4 : 4 : 4, YUV 4 : 4 : 4, YUV 4 : 2 : 2 ITU-R BT.656 or YUV 4 : 2 : 2  
semi-planar standard on output bus  
I Integrated downsampling-by-two with selectable filters on CB and CR channels in the  
4 : 2 : 2 mode  
I IC controlled via the I2C-bus, 5 V tolerant and bit rate up to 400 kbit/s  
 
 

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