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TDA8002BT/3/C2-T PDF预览

TDA8002BT/3/C2-T

更新时间: 2024-01-26 08:42:46
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管外围集成电路
页数 文件大小 规格书
28页 131K
描述
IC SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, Microprocessor IC:Other

TDA8002BT/3/C2-T 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.6JESD-30 代码:R-PDSO-G28
长度:17.9 mm端子数量:28
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:6.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

TDA8002BT/3/C2-T 数据手册

 浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第4页浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第5页浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第6页浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第8页浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第9页浏览型号TDA8002BT/3/C2-T的Datasheet PDF文件第10页 
Philips Semiconductors  
Product specification  
IC card interface  
TDA8002  
FUNCTIONAL DESCRIPTION  
Power supply  
Clock circuitry  
The TDA8002 supports both synchronous and  
asynchronous cards (I2C-bus memories requiring an  
acknowledge signal from the master are not supported).  
There are three methods to clock the circuitry:  
The supply pins for the chip are VDDA, VDDD, AGND,  
DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be  
in the range of 3.0 to 6.5 V. All card contacts remain  
inactive during power-up or power-down.  
Apply a clock signal to pin STROBE  
Use of an internal RC oscillator  
On power-up, the logic is reset by an internal signal.  
The sequencer is not activated until VDD reaches  
Vth2 + Vhys2 (see Fig.5). When VDD falls below Vth2, an  
automatic deactivation sequence of the contacts is  
performed.  
Use of a quartz oscillator which should be connected  
between pins XTAL1 and XTAL2.  
When CLKSEL is HIGH, the clock should be applied on the  
STROBE pin, and when CLKSEL is LOW, one of the  
internal oscillators is used.  
Supply voltage supervisor (VDD  
)
When an internal clock is used, the clock output is  
available on pin CLKOUT. The RC oscillator is selected by  
making CLKDIV1 HIGH and CLKDIV2 LOW. The clock  
output to the card is available on pin CLK. The frequency  
of the card clock can be the input frequency divided by  
2 or 4, STOP LOW or 1.25 MHz, depending on the states  
of CLKDIV1 or CLKDIV2 (see Table 1).  
This block surveys the VDD supply. A defined reset pulse  
of 10 ms minimum (tW) can be retriggered and is delivered  
on the ALARM outputs during power-up or power-down of  
VDD (see Fig.5). This signal is also used for eliminating the  
spikes on card contacts during power-up or power-down.  
When VDD reaches Vth2 + Vhys2, an internal delay is  
started. The ALARM outputs are active until this delay has  
expired. When VDD falls below Vth2, ALARM is activated  
and a deactivation sequence of the contacts is performed.  
Do not change CLKSEL during activation. When in  
low-power (sleep) mode, the internal oscillator frequency  
which is available on pin CLKOUT is lowered to  
approximately 16 kHz for power-economy purposes.  
For 3 V supply, the supervisor option must be chosen at  
3 V. For 5 V supply, both options (3 or 5 V) may be chosen  
depending on the application.  
V
V
+ V  
hys2  
th2  
th2  
V
DD  
t
t
W
W
ALARM  
ALARM  
MGE734  
Fig.5 Alarm as a function of VDD (pulse width 10 ms).  
1997 Nov 04  
7

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