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TD351IDT PDF预览

TD351IDT

更新时间: 2024-02-10 03:30:18
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动器双极性晶体管
页数 文件大小 规格书
12页 158K
描述
Advanced IGBT/MOSFET Driver

TD351IDT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP8,.3
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82内置保护:OVER CURRENT; UNDER VOLTAGE
接口集成电路类型:HALF BRIDGE BASED PERIPHERAL DRIVERJESD-30 代码:R-PDIP-T8
JESD-609代码:e3功能数量:1
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C输出电流流向:SOURCE AND SINK
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:16 V认证状态:Not Qualified
子类别:MOSFET Drivers最大供电电压:26 V
标称供电电压:16 V表面贴装:NO
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
断开时间:0.4 µs接通时间:2.2 µs
宽度:7.62 mm

TD351IDT 数据手册

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Functional Description  
TD351  
4 Functional Description  
4.1 Input stage  
4.4 Two level turn-off  
TD351 input is compatible with optocouplers or  
pulse transformers. The input is triggered by the  
signal edge and allows the use of low-sized, low-  
cost pulse transformer. Input is active low: output  
is driven high when input is driven low. The IN  
input is internally clamped at about 5V to 7V.  
During turn-off, gate voltage can be reduced to a  
programmable level in order to reduce the IGBT  
current (in the event of over-current). This action  
avoids both dangerous overvoltage across the  
IGBT, and RBSOA problems, especially at short  
circuit turn-off.  
When using an open collector optocoupler, the  
resistive pull-up resistor can be connected to  
either VREF or VH. Recommended pull-up  
resistor value with VH=16V are from 4.7k to 22k.  
When driven by a pulse transformer, the input  
positive and negative pulse widths at the Vton and  
Vtoff threshold voltages must be larger than the  
Turn-off (T ) delay is programmable through  
a
external resistor R and capacitor C for accurate  
d
d
timing. T is approximately given by:  
a
T (µs) = 0.7. R (kOhms). C (nF)  
a
d
d
Turn-off delay (T ) is also used to delay the input  
a
signal to prevent distortion of input pulse width.  
The Two level turn-off sequence can be disabled  
by connecting LVOFF pin to VH and connecting  
CD pin to VREF with a 4.7k resistor.  
minimum pulse width t  
(see fig. 4). This  
onmin  
feature acts as a filter against invalid input pulses  
smaller than t  
.
onmin  
4.5 Minimum Input ON-time  
4.2 Voltage reference  
Input signals with ON-time smaller than T are  
a
A voltage reference is used to create accurate  
timing for the turn-on delay with external resistor  
and capacitor. The same circuitry is also used for  
the two-level turn-off delay.  
ignored. ON-time signals larger than T +2.R .C  
a del d  
(R is the internal discharge switch resistance,  
del  
C is the external timing capacitor) are transmitted  
d
to the output stage after the T delay with  
a
A decoupling capacitor (10nF to 100nF) on VREF  
pin is required to ensure good noise rejection.  
minimum width distortion (T =T  
-T ). For  
w
wout win  
ON-time input signals close to T (between T and  
a
a
T +2.R .C ), the 2-level duration is slightly  
reduced and the total output width can be smaller  
than the input width (see fig. 5).  
a
del  
d
4.3 Active Miller clamp:  
The TD351 offers an alternative solution to the  
problem of the Miller current in IGBT switching  
applications. Instead of driving the IGBT gate to a  
negative voltage to increase the safety margin,  
the TD351 uses a dedicated CLAMP pin to control  
the Miller current. When the IGBT is off, a low  
impedance path is established between IGBT  
gate and emitter to carry the Miller current, and  
the voltage spike on the IGBT gate is greatly  
reduced.  
During turn-off, the gate voltage is monitored and  
the clamp output is activated when gate voltage  
goes below 2V (relative to VL). The clamp voltage  
is VL+4V max for a Miller current up to 500mA.  
The clamp is disabled when the IN input is  
triggered again.  
4.6 Output stage  
The output stage is able to sink/source 1.7A/1.3A  
typical at 25°C and 1.0A/0.75A min. over the full  
temperature range. This current capability is  
specified near the usual IGBT Miller plateau.  
4.7 Undervoltage protection  
Undervoltage detection protects the application in  
the event of a low VH supply voltage (during start-  
up or a fault situation). During undervoltage, the  
OUT pin is driven low (active pull-down for  
VH>2V, passive pull-down for VH<2V.  
UVH  
UVL  
Vccmin  
VH  
The CLAMP function doesnt affect the turn-off  
characteristic, but only keeps the gate to the low  
level throughout the off time. The main benefit is  
that negative voltage can be avoided in many  
cases, allowing a bootstrap technique for the high  
side driver supply.  
2V  
OUT  
FAULT  
5/12  

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