Functional Description
TD351
4 Functional Description
4.1 Input stage
4.4 Two level turn-off
TD351 input is compatible with optocouplers or
pulse transformers. The input is triggered by the
signal edge and allows the use of low-sized, low-
cost pulse transformer. Input is active low: output
is driven high when input is driven low. The IN
input is internally clamped at about 5V to 7V.
During turn-off, gate voltage can be reduced to a
programmable level in order to reduce the IGBT
current (in the event of over-current). This action
avoids both dangerous overvoltage across the
IGBT, and RBSOA problems, especially at short
circuit turn-off.
When using an open collector optocoupler, the
resistive pull-up resistor can be connected to
either VREF or VH. Recommended pull-up
resistor value with VH=16V are from 4.7k to 22k.
When driven by a pulse transformer, the input
positive and negative pulse widths at the Vton and
Vtoff threshold voltages must be larger than the
Turn-off (T ) delay is programmable through
a
external resistor R and capacitor C for accurate
d
d
timing. T is approximately given by:
a
T (µs) = 0.7. R (kOhms). C (nF)
a
d
d
Turn-off delay (T ) is also used to delay the input
a
signal to prevent distortion of input pulse width.
The Two level turn-off sequence can be disabled
by connecting LVOFF pin to VH and connecting
CD pin to VREF with a 4.7k resistor.
minimum pulse width t
(see fig. 4). This
onmin
feature acts as a filter against invalid input pulses
smaller than t
.
onmin
4.5 Minimum Input ON-time
4.2 Voltage reference
Input signals with ON-time smaller than T are
a
A voltage reference is used to create accurate
timing for the turn-on delay with external resistor
and capacitor. The same circuitry is also used for
the two-level turn-off delay.
ignored. ON-time signals larger than T +2.R .C
a del d
(R is the internal discharge switch resistance,
del
C is the external timing capacitor) are transmitted
d
to the output stage after the T delay with
a
A decoupling capacitor (10nF to 100nF) on VREF
pin is required to ensure good noise rejection.
minimum width distortion (∆T =T
-T ). For
w
wout win
ON-time input signals close to T (between T and
a
a
T +2.R .C ), the 2-level duration is slightly
reduced and the total output width can be smaller
than the input width (see fig. 5).
a
del
d
4.3 Active Miller clamp:
The TD351 offers an alternative solution to the
problem of the Miller current in IGBT switching
applications. Instead of driving the IGBT gate to a
negative voltage to increase the safety margin,
the TD351 uses a dedicated CLAMP pin to control
the Miller current. When the IGBT is off, a low
impedance path is established between IGBT
gate and emitter to carry the Miller current, and
the voltage spike on the IGBT gate is greatly
reduced.
During turn-off, the gate voltage is monitored and
the clamp output is activated when gate voltage
goes below 2V (relative to VL). The clamp voltage
is VL+4V max for a Miller current up to 500mA.
The clamp is disabled when the IN input is
triggered again.
4.6 Output stage
The output stage is able to sink/source 1.7A/1.3A
typical at 25°C and 1.0A/0.75A min. over the full
temperature range. This current capability is
specified near the usual IGBT Miller plateau.
4.7 Undervoltage protection
Undervoltage detection protects the application in
the event of a low VH supply voltage (during start-
up or a fault situation). During undervoltage, the
OUT pin is driven low (active pull-down for
VH>2V, passive pull-down for VH<2V.
UVH
UVL
Vccmin
VH
The CLAMP function doesn’t affect the turn-off
characteristic, but only keeps the gate to the low
level throughout the off time. The main benefit is
that negative voltage can be avoided in many
cases, allowing a bootstrap technique for the high
side driver supply.
2V
OUT
FAULT
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