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T436416A-7.5S PDF预览

T436416A-7.5S

更新时间: 2024-11-24 22:42:31
品牌 Logo 应用领域
TMT 动态存储器
页数 文件大小 规格书
29页 710K
描述
4M X 16 SDRAM

T436416A-7.5S 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:TSOP2, TSOP54,.46,32Reach Compliance Code:unknown
风险等级:5.48访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0长度:22.22 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.125 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

T436416A-7.5S 数据手册

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TE  
tmCH  
T436416A  
4M x 16 SDRAM  
SDRAM  
1M x 16bit x 4Banks Synchronous DRAM  
FEATURES  
GRNERAL DESCRIPTION  
3.3V power supply  
Four banks operation  
LVTTL compatible with multiplexed address  
All inputs are sampled at the positive going  
edge of system clock  
The T436416A is 67,108,864 bits synchronous  
high data rate Dynamic RAM organized as  
4 x 1,048,576 words by 16 bits , fabricated with  
high performance CMOS technology .  
Synchronous design allows precise cycle control  
with the use of system clock I/O transactions are  
possible on every clockcycle . Range of operating  
frequencies , programmable burst length and  
programmable latencies allow the same device to  
be useful for a variety of high bandwidth , high  
performance memory system applications.  
Burst Read Single-bit Write operation  
DQM for masking  
Auto refresh and self refresh  
64ms refresh period (4K cycle)  
MRS cycle with address key programs  
- CAS Latency ( 2 & 3 )  
- Burst Length ( 1 , 2 , 4 , 8 & full page)  
- Burst Type (Sequential & Interleave)  
Available package type in 54 pin TSOP(II)  
Operating temperature : 0 ~ +70 °C  
PIN ARRANGEMENT (Top View)  
ORDERING INFORMATION  
V
D
D
V s s  
1
5 4  
5 3  
5 2  
5 1  
5 0  
4 9  
4 8  
4 7  
4 6  
4 5  
4 4  
4 3  
4 2  
4 1  
4 0  
3 9  
3 8  
3 7  
MAX  
D Q 0  
D Q 1 5  
2
PACKAGE  
PART NO.  
V
D
D
Q
V S S Q  
3
FREQUENCY  
D Q 1  
D Q 2  
D Q 1 4  
D Q 1 3  
4
54 pin TSOP(II)  
54 pin TSOP(II)  
54 pin TSOP(II)  
54 pin TSOP(II)  
54 pin TSOP(II)  
T436416A-6S  
T436416A-7S  
T436416A-7.5S  
T436416A-8S  
T436416A-10S  
166 MHz  
5
V
S S Q  
D Q 3  
D Q 4  
V D D Q  
6
143 MHz  
133 MHz  
125 MHz  
100 MHz  
D Q 1 2  
D Q 1 1  
V
7
8
V
D D Q  
S S Q  
9
D Q 5  
D Q 6  
D Q 1 0  
D Q 9  
V
1 0  
1 1  
1 2  
V
S S Q  
D
D
Q
5 4 P I N T S O P ( II)  
( 4 0 0 m il 8 7 5 m il )  
( 0 .8 m m P IN P IT C H )  
x
54 pin TSOP(II)  
lead-free  
54 pin TSOP(II)  
lead-free  
1 3  
1 4  
D Q 7  
D Q 8  
V s s  
T436416A-6SG  
T436416A-7SG  
166 MHz  
143 MHz  
V
D D  
N .C / R F U  
U D Q M  
C L K  
C K E  
N .C  
L D Q M  
1 5  
1 6  
1 7  
1 8  
1 9  
2 0  
2 1  
2 2  
2 3  
2 4  
2 5  
2 6  
2 7  
W
E
C A S  
R A S  
C S  
54 pin TSOP(II)  
lead-free  
T436416A-7.5SG 133 MHz  
3 6  
3 5  
3 4  
3 3  
3 2  
3 1  
3 0  
2 9  
2 8  
B A 0  
B A 1  
A 1 0 / A P  
A 0  
A 1 1  
A 9  
54 pin TSOP(II)  
lead-free  
54 pin TSOP(II)  
lead-free  
T436416A-8SG  
T436416A-10SG  
125 MHz  
100 MHz  
A 8  
A 7  
A 1  
A 6  
A 2  
A 5  
A 3  
A 4  
V
D
D
V s s  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 1  
Publication Date: MAY. 2003  
Revision: B  

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