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tmCH
T436416C
4M x 16 SDRAM
SDRAM
1M x 16bit x 4Banks Synchronous DRAM
FEATURES
GRNERAL DESCRIPTION
• 3.3V power supply
• Four banks operation
• LVTTL compatible with multiplexed address
• All inputs are sampled at the positive going
edge of system clock
The T436416C is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 1,048,576 words by 16 bits , fabricated with
high performance CMOS technology .
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth, high
performance memory system applications.
• DQM for masking
• Auto refresh and self refresh
• 64ms refresh period
• 15.6 us refresh interval.
• MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
• Available package type in 54 pin TSOP(II)
• Operating temperature : 0 ~ +70 °C
PIN ARRANGEMENT (Top View)
ORDERING INFORMATION
V
D
D
V s s
1
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
MAX
D Q 0
D Q 1 5
2
PACKAGE
PART NO.
FREQUENCY
V
D
D
Q
V S S Q
3
D Q 1
D Q 2
D Q 1 4
D Q 1 3
4
54 pin TSOP(II)
54 pin TSOP(II)
T436416C-6S
T436416C-7S
166 MHz
5
V
S S Q
D Q 3
D Q 4
V D D Q
6
143 MHz
166 MHz
D Q 1 2
D Q 1 1
V
7
54 pin TSOP(II)
lead-free
54 pin TSOP(II)
lead-free
8
T436416C-6SG
T436416C-7SG
V
D D Q
S S Q
9
D Q 5
D Q 6
D Q 1 0
D Q 9
V
1 0
143 MHz
1 1
1 2
V
S S Q
D
D
Q
5 4 P I N T S O P ( II)
( 4 0 0 m il 8 7 5 m il )
( 0 .8 m m P IN P IT C H )
x
1 3
1 4
D Q 7
D Q 8
V s s
V
D D
N .C / R F U
U D Q M
C L K
C K E
N .C
L D Q M
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
W
E
C A S
R A S
C S
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
A 1 3
A 1 2
A 1 0 / A P
A 0
A 1 1
A 9
A 8
A 7
A 1
A 6
A 2
A 5
A 3
A 4
V
D
D
V s s
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: AUG. 2004
Revision: A