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T436416D PDF预览

T436416D

更新时间: 2024-11-01 03:29:43
品牌 Logo 应用领域
TMT 动态存储器
页数 文件大小 规格书
73页 710K
描述
4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM

T436416D 数据手册

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TE  
tmCH  
T436416D  
4M x 16 SDRAM  
SDRAM  
1M x 16bit x 4Banks Synchronous DRAM  
FEATURES  
GRNERAL DESCRIPTION  
Fast access time from clock: 4.5/5/5.4 ns  
Fast clock rate: 200/166/143 MHz  
Fully synchronous operation  
The T436416D SDRAM is a high-speed CMOS  
synchronous DRAM containing 64 Mbits. It is internally  
configured as 4 Banks of 1M word x 16 DRAM with a  
synchronous interface (all signals are registered on the  
positive edge of the clock signal, CLK). Read and write  
accesses to the SDRAM are burst oriented; accesses  
start at a selected location and continue for a  
programmed number of locations in a programmed  
sequence. Accesses begin with the registration of a  
BankActivate command which is then followed by a  
Read or Write command.  
Internal pipelined architecture  
1M word x 16-bit x 4-bank  
Programmable Mode registers  
- CAS# Latency: 2, or 3  
- Burst Length: 1, 2, 4, 8, or full page  
- Burst Type: interleaved or linear burst  
- Burst stop function  
The T436416D provides for programmable Read  
or Write burst lengths of 1, 2, 4, 8, or full page, with a  
burst termination option. An auto precharge function  
may be enabled to provide a self-timed row precharge  
that is initiated at the end of the burst sequence. The  
refresh functions, either Auto or Self Refresh are easy to  
use.  
Auto Refresh and Self Refresh  
4096 refresh cycles/64ms  
CKE power down mode  
Single +3.3V ± 0.3V power supply  
Interface: LVTTL  
54-pin 400 mil plastic TSOP II package  
60-Ball, 6.4 mm x 10.1 mm TFBGA package  
By having a programmable mode register, the  
system can choose the most suitable modes to maximize  
its performance. These devices are well suited for  
applications requiring high memory bandwidth and  
particularly well suited to high performance PC  
applications.  
Key Specifications  
T436416D  
-
5/6/7  
5/6/7 ns  
tCK3 Clock Cycle time(min.)  
tAC3 Access time from CLK(max.)  
tRAS Row Active time(min.)  
tRC Row Cycle time(min.)  
4.5/5/5.4/ ns  
35/42/45 ns  
50/60/63 ns  
ORDERING INFORMATION  
Part Number  
Frequency  
Package  
T436416D-5S/-5C  
200MHz TSOP II / TFBGA  
T436416D-5SG/-5CG 200MHz TSOP II / TFBGA  
T436416D-6S/-6C 166MHz TSOP II / TFBGA  
T436416D-6SG/-6CG 166MHz TSOP II / TFBGA  
T436416D-7S/-7C 143MHz TSOP II / TFBGA  
T436416D-7SG/-7CG 143MHz TSOP II / TFBGA  
S : indicates TSOPII Package,  
C : indicates TFBGA Package,  
G : indicates Pb Free Package  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 1  
Publication Date: FEB. 2007  
Revision: A  

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