T2316405A
TE
Preliminary T2316407A
4M x 4 DYNAMIC RAM
DRAM
EDO PAGE MODE
FEATURES
GRNERAL DESCRIPTION
·
·
·
Industry-standard x 4 pinouts and timing
functions
power supply : T2316405A 2.6V(±0.2V)
T2316407A 3.3V(±0.3V)
All device pins are TTL- compatible.
The T2316405A and T2316407A is a randomly
accessed solid state memory containing 16,777,216
bits organized in a x 4 configuration. It offers Fast
Page mode with Extended Data Output (EDO).
· 2048-cycle refresh in 32 ms.
During READ or WRITE cycles, each of the 4
memory bits (1 bit per I/O) is uniquely addressed
through the 22 address bits, which are entered 11
·
·
RAS
CAS
BEFORE
Refresh modes:
RAS
only,
(CBR) and HIDDEN.
Extended data-out (EDO) PAGE MODE
access cycle.
RAS
bits (A0-A10) at a time.
latches the first 11
latches the latter 11 bits.
A READ or WRITE cycle is selected with
CAS
bits and
OPTION
WE
WE
WE
the
input. A logic HIGH on
dictates
dictates
TIMING
MARKING
READ mode while a logic LOW on
50ns (For T2316407A only)
60ns (For T2316407A only)
70ns (For T2316407A only)
100ns (For T2316405A only)
-50
-60
-70
-10
WRITE mode. During a WRITE cycle, data-in is
latched by the falling edge of WE or CAS ,
WE
whichever occurs last. When
goes Low prior
to CAS going LOW ( EARLY WRITE cycle), the
output pins remain open (High-Z) until the next
PACKAGE
26/24-pin SOJ
J
26/24-pin TSOP-II
S
CAS
cycle.
A Late Write or Read-Modify-Write occurs.
When WE falls after CAS was taken LOW (Late
PIN ARRANGEMENT (
Top View)
1
2
3
4
5
6
26
25
24
23
22
21
Vss
I/O4
I/O3
CAS
OE
Vcc
I/O1
I/O2
WE
OE
must be taken HIGH to disable
Write cycle).
the data-outputs prior to applying input data.
The four data inputs and four data outputs are
routed through four pins using common I/O, and pin
RAS
NC
SOJ
&
A9
WE
OE
and .
direction is controlled by
TSOP-II
A10
A0
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
Vss
9
10
11
12
13
A1
A2
A3
Vcc
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: APR 2001
Revision:0.B