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SY100EP14U

更新时间： 2024-11-04 22:40:47
品牌 Logo 应用领域
麦瑞 - MICREL 时钟驱动器输入元件
页数 文件大小 规格书
9页 73K
描述
2.5V/3.3V/5V 1:5 LVPECL/PECL/ ECL/HSTL 2GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX

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中文翻译

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SY100EP14U 数据手册

 浏览型号SY100EP14U的Datasheet PDF文件第2页浏览型号SY100EP14U的Datasheet PDF文件第3页浏览型号SY100EP14U的Datasheet PDF文件第4页浏览型号SY100EP14U的Datasheet PDF文件第5页浏览型号SY100EP14U的Datasheet PDF文件第6页浏览型号SY100EP14U的Datasheet PDF文件第7页 
2.5V/3.3V/5V 1:5 LVPECL/PECL/  
ECL/HSTL 2GHz CLOCK DRIVER  
WITH 2:1 DIFFERENTIAL INPUT MUX  
Precision Edge™  
SY100EP14U  
FEATURES  
■ Guaranteed AC parameters over temp/voltage:  
ECL Pro™  
• > 2GHz fMAX  
• < 25ps within-device skew  
• < 275ps tr/tf time  
• < 525ps prop delay  
DESCRIPTION  
The SY100EP14U is a high-speed, 2GHz differential  
PECL/ECL 1:5 fanout buffer optimized for ultra-low skew  
applications. Within device skew is guaranteed to be less  
than 25ps over temperature and supply voltage. The wide  
supply voltage operation allows this fanout buffer to operate  
■ 2:1 Differential Mux input  
■ Flexible supply voltage: 2.5V/3.3V/5V  
■ Wide operating temperature range: –40°C to +85°C  
■ V reference for single-ended or AC-coupled  
BB  
PECL inputs  
in 2.5V, 3.3V, and 5V systems. A V reference is included  
BB  
for single-supply or AC-coupled PECL/ECL input  
applications, thus eliminating resistor networks. When  
interfacing to a single-ended or AC-coupled PECL/ECL input  
■ 100K ECL compatible outputs  
■ Inputs accept PECL/LVPECL/ECL/HSTL logic  
■ 75kΩ internal input pull-down resistors  
■ Available in a 20-Pin TSSOP package  
signal, connect the V  
pin to the unused /CLK pin, and  
BB  
bypass the pin to V through a 0.01µF capacitor.  
CC  
The SY100EP14U features a 2:1 input MUX, making it  
an ideal solution for redundant clock switchover applications.  
If only one input pair is used, the other pair may be left  
floating. In addition, this device includes a synchronous  
enable pin that forces the outputs into a fixed logic state.  
Enable or disable state is initiated only after the outputs are  
in a LOW state, thus eliminating the possibility of a “runt”  
clock pulse.  
PIN CONFIGURATION/BLOCK DIAGRAM  
/CLK1  
VBB  
CLK0  
/CLK0 SEL VEE  
VCC /EN VCC  
CLK1  
20 19 18 17 16 15 14 13 12 11  
The SY100EP14U I/O are fully differential and 100K ECL  
compatible. Differential 10K ECL logic can interface directly  
into the SY100EP14U inputs.  
D
Q
1
0
The SY100EP14U is part of Micrel’s high-speed clock  
synchronization family. For applications that require a  
different I/O combination, consult the Micrel website at  
www.micrel.com, and choose from a comprehensive product  
line of high-speed, low-skew fanout buffers, translators, and  
clock generators.  
1
2
3
4
5
6
7
8
9
10  
Q0 /Q0 Q1 /Q1 Q2 /Q2 Q3 /Q3 Q4 /Q4  
TSSOP  
TOP VIEW  
Precision Edge and ECL Pro are trademarks of Micrel, Inc.  
Rev.: D  
Amendment: /0  
1
Issue Date: July 2003  
1234567...9

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