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STR730FZ2T7 PDF预览

STR730FZ2T7

更新时间: 2024-09-15 22:08:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微控制器和处理器外围集成电路闪光灯PC时钟
页数 文件大小 规格书
22页 383K
描述
ARM7TDMI 32-BIT MCU WITH FLASH, 3x CAN, 4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES

STR730FZ2T7 技术参数

是否Rohs认证:符合生命周期:Not Recommended
零件包装代码:QFP包装说明:LFQFP, QFP144,.87SQ,20
针数:144Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
Factory Lead Time:12 weeks风险等级:5.71
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:4625Samacsys Pin Count:144
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat Packages
Samacsys Footprint Name:STR730FZ2T7Samacsys Released Date:2015-04-16 09:48:08
Is Samacsys:N具有ADC:YES
地址总线宽度:位大小:32
CPU系列:ARM7最大时钟频率:8 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PQFP-G144
JESD-609代码:e3长度:20 mm
湿度敏感等级:3I/O 线路数量:112
端子数量:144片上程序ROM宽度:8
最高工作温度:105 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not QualifiedRAM(字节):16384
ROM(单词):262144ROM可编程性:FLASH
座面最大高度:1.6 mm速度:36 MHz
子类别:Microcontrollers最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:20 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

STR730FZ2T7 数据手册

 浏览型号STR730FZ2T7的Datasheet PDF文件第2页浏览型号STR730FZ2T7的Datasheet PDF文件第3页浏览型号STR730FZ2T7的Datasheet PDF文件第4页浏览型号STR730FZ2T7的Datasheet PDF文件第5页浏览型号STR730FZ2T7的Datasheet PDF文件第6页浏览型号STR730FZ2T7的Datasheet PDF文件第7页 
STR73xF  
ARM7TDMI32-BIT MCU WITH FLASH, 3x CAN,  
4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES  
DATA BRIEF  
Core  
– ARM7TDMI 32-bit RISC CPU  
– 32 MIPS @ 36 MHz  
Temperature Range  
– Operating temperature range -40 to 105 °C  
Memories  
TQFP100 14 x 14  
– Up to 256 Kbytes FLASH program memory  
(10,000 cycles endurance, data retention 20  
years at 55°C)  
TQFP144  
20 x 20  
– 16 Kbytes RAM  
LFBGA144 10 x 10 x 1.7  
Clock, Reset and Supply Management  
– 4.5 - 5.5V application supply and I/O interface  
– Embedded 1.8V regulator for core supply  
DMA  
– 4 DMA controllers with 4 channels each  
Timers  
– Embedded oscillator running from external  
4-8MHz crystal or ceramic resonator  
– 16-bit watchdog timer (WDG)  
– Up to 36 MHz CPU freq. with internal PLL  
– 6/10 16-bit timers (TIM) each with: 2 input  
captures, 2 output compares, PWM and pulse  
counter modes  
– Internal RC oscillator 32kHz or 2MHz soft-  
ware configurable for fast startup and backup  
clock  
– 6 16-bit PWM modules (PWM)  
– Realtime Clock for clock-calendar function  
– 3 16-bit timebase timers with 8-bit prescalers  
12 Communications Interfaces  
– Wakeup Timer driven by internal RC for wake-  
up from STOP mode  
2
– 5 power saving modes: SLOW, WAIT,  
LPWAIT, STOP and HALT modes  
Nested interrupt controller  
– 2 I C interfaces  
– 4 UART asynchronous serial communications  
interfaces  
– Fast interrupt handling with multiple vectors  
– 3 BSPI synchronous serial interfaces  
– Up to 3 CAN interfaces (2.0B Active)  
10-bit A/D Converter  
– 12/16 channels  
– Conversion time: min 3µs, range: 0 to 5V  
Development Tools Support  
– 64 maskable IRQ with 64 vectors and  
16 priority levels  
– 2 maskable FIQ sources  
– 16 external interrupts and up to 32 wake up  
lines  
Up to 112 I/O ports  
– JTAG interface  
– 72/112 multifunctional bidirectional I/O lines  
Table 1. Device Summary  
Features  
FLASH memory - bytes  
STR730FZx  
128K 256K  
16K  
STR735FZx  
128K 256K  
STR731FVx  
STR736FVx  
64K  
128K  
256K  
16K  
64K  
128K  
256K  
RAM - bytes  
6 TIM Timers, 72 I/Os, 18 Wake-Up lines,  
12 ADC channels  
10 TIM Timers, 112 I/Os, 32  
Wake-Up lines, 16 ADC channels  
Peripheral Functions  
CAN Peripherals  
3
0
3
0
Operating Voltage  
Operating Temperature  
4.5 to 5.5V (optional 1.8V for core)  
-40 to +105°C  
T=TQFP144 20 x 20  
H=LFBGA144 10 x10  
Packages  
T=TQFP100 14x14  
Rev. 1  
July 2005  
1/22  
This is preliminary information on a new product now in development. Details are subject to change without notice.  
1

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