Datasheet > STPCD01

STPCD01

更新时间： 2024-11-24 23:35:19

品牌	Logo	应用领域
其他 - ETC		微处理器 PC
页数	文件大小	规格书
61页	1006K
描述
STPC CLIENT DATASHEET / PC COMPATIBLE EMBEDED MICROPROCESSOR

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中文翻译

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数据手册

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STPCD01 数据手册

STPC_®CLIENT

PC Compatible Embedded Microprocessor

•

POWERFUL X86 PROCESSOR

64-BIT 66MHz BUS INTERFACE

64-BIT DRAM CONTROLLER

SVGA GRAPHICS CONTROLLER

UMA ARCHITECTURE

VIDEO SCALER

VIDEO OUTPUT PORT

VIDEO INPUT PORT

CRT CONTROLLER

135MHz RAMDAC

PBGA388

2 OR 3 LINE FLICKER FILTER

SCAN CONVERTER

Figure 1. Logic Diagram

PCI MASTER / SLAVE / ARBITER

ISA MASTER/SLAVE

ISA BUS

IDE CONTROLLER

x86

Core

DMA CONTROLLER

ISA

PCI

IPC

EID

INTERRUPT CONTROLLER

TIMER / COUNTERS

Host I/F

POWER MANAGEMENT

EIDE

PCI BUS

CCIR Input

STPC CLIENT OVERVIEW

PCI

VIP

The STPC Client integrates a standard 5th

generation x86 core, a DRAM controller, a

graphics subsystem,

support logic including PCI, ISA, and IDE

controllers to provide single Consumer

video pipeline, and

TV Output

orientated PC compatible subsystem on a single

device.

Anti-

Col-

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

colour space conversion of the video input stream

and mixing of the video stream with non-video

data from the frame buffer. The chip also includes

anti-flicker filters to provide a stable, high-quality

Digital TV output.

Vid-

Col-

our

Monitor

CRT

SYNC Output

DRAM

The STPC Client is packaged in a 388 Plastic Ball

Grid Array (PBGA).

October 13, 2000

Issue 2.2

1/61

12 3 4 5 6 7...61

中文翻译

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