Datasheet > STPC4HEBI

STPC4HEBI

更新时间： 2024-11-24 22:16:07

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		PC
页数	文件大小	规格书
93页	1403K
描述
X86 Core PC Compatible Information Appliance System-on-Chip

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中文翻译

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数据手册

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STPC4HEBI 数据手册

STPC CONSUMER-II

X86 Core PC Compatible Information Appliance System-on-Chip

■

POWERFUL x86 PROCESSOR

64-BIT SDRAM UMA CONTROLLER

VGA & SVGA CRT CONTROLLER

135 MHz RAMDAC

2D GRAPHICS ENGINE

VIDEO INPUT PORT

VIDEO PIPELINE

- UP-SCALER

- VIDEO COLOUR SPACE CONVERTER

- CHROMA & COLOUR KEY SUPPORT

PBGA388

■

TV OUTPUT

- THREE-LINE FLICKER FILTER

- ITU-R 601/656 SCAN CONVERTER

- NTSC / PAL COMPOSITE, RGB, S-VIDEO

Figure 0-1. Logic Diagram

■

PCI MASTER / SLAVE / ARBITER

ISA MASTER / SLAVE

Host x86

I/F

Core

OPTIONAL 16-BIT LOCAL BUS INTERFACE

EIDE CONTROLLER

PCI Bus

PCI

m/s

PMU

I²C INTERFACE

IPC

IDE

I/F

ISA

m/s

PCI

m/s

IPC

- DMA CONTROLLER

- INTERRUPT CONTROLLER

- TIMER / COUNTERS

ISA Bus

CTR

Local Bus

■

POWER MANAGEMENT UNIT

JTAG IEEE1149.1

Video

Pipeline

DESCRIPTION

C Key

K Key

LUT

Monitor

The STPC Consumer-II integrates a standard 5th

generation x86 core, a Synchronous DRAM

controller, a graphics subsystem, a video pipeline,

and support logic including PCI, ISA, and IDE

SVGA

CRTC

TVO

Cursor

Encoder

controllers to provide

single consumer

orientated PC compatible subsystem on a single

device.

VIP

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing memory

between the CPU, the graphics and the video.

SDRAM

CTRL

JTAG

The STPC Consumer-II is packaged in a 388

Plastic Ball Grid Array (PBGA).

Release 1.5 - January 29, 2002

1/93

12 3 4 5 6 7...93

中文翻译

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