STK14C88
32K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
The Simtek STK14C88 is a fast static RAM with a
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic STORE with External
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in the nonvolatile elements.
Data transfers from the SRAM to the nonvolatile ele-
ments (the STORE operation) can take place auto-
matically on power down. A 68µF or larger capacitor
tied from VCAP to ground guarantees the STORE
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the nonvolatile elements to the SRAM (the RECALL
operation) take place automatically on restoration of
power. Initiation of STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
68µF Capacitor on Power Down
• STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStore™
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to nonvolatile ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 5V + 10% Operation
• Commercial, Industrial and Military Tempera-
tures
• 32-Pin SOIC, DIP and LCC Packages
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
2
V
CCX
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CAP
A
V
V
CAP
CCX
HSB
14
12
A
3
4
5
6
7
8
9
10
11
12
13
14
15
16
W
A
A
7
6
5
4
3
13
Quantum Trap
512 x 512
A
A
8
A
A
A
A
POWER
9
11
A
CONTROL
A5
G
NC
A6
NC
A
STORE
A
E
2
10
A7
A
1
0
STORE/
RECALL
A8
STATIC RAM
A
DQ
DQ
7
6
5
4
3
HSB
RECALL
A9
ARRAY
DQ
0
CONTROL
DQ
DQ
DQ
DQ
1
2
512 x 512
A11
A12
A13
A14
DQ
V
SS
32 - DIP
32 - LCC
32 - SOIC
SOFTWARE
DETECT
A
- A
13
0
DQ
DQ
DQ
PIN NAMES
0
1
2
COLUMN I/O
A
- A
Address Inputs
Data In/Out
0
14
COLUMN DEC
DQ -DQ
0
7
DQ
3
4
DQ
E
W
G
Chip Enable
Write Enable
Output Enable
DQ
DQ
DQ
5
6
7
A
A A A A A
1 2 3 4 10
0
G
HSB
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
E
W
V
V
V
CCX
CAP
SS
Ground
December 2002
1
Document Control # ML0014 rev 0.0