Datasheet > STK12C68_11

STK12C68_11

更新时间： 2022-09-24 17:04:22

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储静态存储器
页数	文件大小	规格书
24页	1629K
描述
64 Kbit (8K x 8) AutoStore nvSRAM 25 ns, 35 ns, and 45 ns access times

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STK12C68_11 数据手册

STK12C68

Pin Configurations

Figure1. 28-Pin SOIC/DIPandLLC

Pin Definitions

Pin Name Alt

A₀–A₁₂

I/O Type

Input

Input or Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.

Description

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

DQ₀-DQ₇

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O

pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE HIGH causes the I/O pins to tristate.

V_SS

V_CC

Ground

Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

HSB

V_CAP

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-51027 Rev. *C

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型号	品牌	描述	获取价格	数据表
STK12C68-40M	ETC	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM	获取价格
STK12C68-45M	ETC	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM	获取价格
STK12C68-5	CYPRESS	64 Kbit (8K x 8) AutoStore nvSRAM	获取价格
STK12C68-55M	ETC	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM	获取价格
STK12C68-5C25	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格