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STK12C68-5K25M PDF预览

STK12C68-5K25M

更新时间: 2024-10-27 23:11:03
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
13页 371K
描述
8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM

STK12C68-5K25M 数据手册

 浏览型号STK12C68-5K25M的Datasheet PDF文件第2页浏览型号STK12C68-5K25M的Datasheet PDF文件第3页浏览型号STK12C68-5K25M的Datasheet PDF文件第4页浏览型号STK12C68-5K25M的Datasheet PDF文件第6页浏览型号STK12C68-5K25M的Datasheet PDF文件第7页浏览型号STK12C68-5K25M的Datasheet PDF文件第8页 
STK12C68  
HARDWARE MODE SELECTION  
E
H
L
W
X
H
L
HSB  
A
- A (hex)  
0
MODE  
Not Selected  
I/O  
POWER  
NOTES  
12  
H
X
X
X
X
Output High Z  
Output Data  
Input Data  
Standby  
Active  
H
Read SRAM  
o
L
H
Write SRAM  
Active  
X
X
L
Nonvolatile STORE  
Output High Z  
l
m
CC  
2
0000  
1555  
0AAA  
1FFF  
10F0  
0F0F  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Read SRAM  
Active  
L
L
H
H
H
H
n, o  
n, o  
Read SRAM  
Read SRAM  
Nonvolatile STORE  
l
CC  
2
0000  
1555  
0AAA  
1FFF  
10F0  
0F0E  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Read SRAM  
Active  
Read SRAM  
Read SRAM  
Nonvolatile RECALL  
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,  
the part will go into standby mode, inhibiting all operations until HSB rises.  
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.  
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.  
HARDWARE STORE CYCLE  
(VCC = 5.0V ± 10%)e  
SYMBOLS  
STK12C68  
NO.  
PARAMETER  
UNITS NOTES  
Standard  
Alternate  
MIN  
MAX  
22  
23  
24  
25  
26  
t
t
t
t
t
t
t
t
STORE Cycle Duration  
10  
ms  
µs  
ns  
ns  
ns  
i, p  
i, q  
p, r  
STORE  
DELAY  
RECOVER  
HLHX  
HLHZ  
HLQZ  
HHQX  
Time Allowed to Complete SRAM Cycle  
Hardware STORE High to Inhibit Off  
Hardware STORE Pulse Width  
1
700  
300  
15  
Hardware STORE Low to Store Busy  
HLBL  
Note p: E and G low for output behavior.  
Note q: E and G low and W high for output behavior.  
Note r: RECOVER is only applicable after tSTORE is complete.  
t
HARDWARE STORE CYCLE  
25  
t
HLHX  
HSB (IN)  
24  
t
RECOVER  
22  
t
STORE  
26  
t
HLBL  
HSB (OUT)  
HIGH IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
23  
t
DELAY  
DQ (DATA OUT)  
DATA VALID  
October 2003  
5
Document Control # ML0008 rev 0.4  
 

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