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STK12C68-5C55M PDF预览

STK12C68-5C55M

更新时间： 2024-02-02 11:20:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
18页 575K
描述
64 Kbit (8K x 8) AutoStore nvSRAM

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STK12C68-5C55M 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：WDIP, DIP28,.3Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：8.66Is Samacsys：N
最长访问时间：35 ns其他特性：RETENTION/ENDURANCE = 10 YEARS/100000 CYCLES
JESD-30 代码：R-CDIP-T28JESD-609代码：e0
长度：35.56 mm内存密度：65536 bit
内存集成电路类型：NON-VOLATILE SRAM内存宽度：8
功能数量：1端口数量：1
端子数量：28字数：8192 words
字数代码：8000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：8KX8输出特性：3-STATE
可输出：YES封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：WDIP封装等效代码：DIP28,.3
封装形状：RECTANGULAR封装形式：IN-LINE, WINDOW
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：4.14 mm最大待机电流：0.004 A
子类别：SRAMs最大压摆率：0.075 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn85Pb15)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

STK12C68-5C55M 数据手册

 浏览型号STK12C68-5C55M的Datasheet PDF文件第3页浏览型号STK12C68-5C55M的Datasheet PDF文件第4页浏览型号STK12C68-5C55M的Datasheet PDF文件第5页浏览型号STK12C68-5C55M的Datasheet PDF文件第7页浏览型号STK12C68-5C55M的Datasheet PDF文件第8页浏览型号STK12C68-5C55M的Datasheet PDF文件第9页 
STK12C68-5 (SMD5962-94599)  
■ Power up boot firmware routines must rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a  
preset state, best practice is to again rewrite the nvSRAM  
into the desired state as a safeguard against events that  
might flip the bit inadvertently (program bugs, incoming  
inspection routines, and so on).  
Best Practices  
nvSRAM products have been used effectively for over 15  
years. While ease-of-use is one of the product’s main system  
values, experience gained working with hundreds of applica-  
tions has resulted in the following suggestions as best  
practices:  
■ The Vcap value specified in this data sheet includes a  
minimum and a maximum value size. The best practice is to  
meet this requirement and not exceed the maximum Vcap  
value because the higher inrush currents may reduce the  
reliability of the internal pass transistor. Customers who want  
to use a larger Vcap value to make sure there is extra store  
charge must discuss their Vcap size selection with Cypress.  
■ The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites sometimes reprograms these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
The end product’s firmware must not assume that an NV  
array is in a set programmed state. Routines that check  
memory content values to determine first time system config-  
uration, cold or warm boot status, and so on must always  
program a unique NV pattern (for example, complex 4-byte  
pattern of 46 E6 49 53 hex or more random bytes) as part of  
the final system manufacturing test to ensure these system  
routines work consistently.  
Table 1. Hardware Mode Selection  
CE  
H
L
WE  
X
HSB  
H
A12–A0  
Mode  
IO  
Power  
Standby  
Active[3]  
Active  
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
H
H
L
L
H
[1]  
X
X
L
Nonvolatile STORE Output High Z  
ICC2  
[2, 3]  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active ICC2  
Nonvolatile STORE Output High Z  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0E  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active[2, 3]  
Nonvolatile RECALL Output High Z  
Notes  
1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby  
mode, inhibiting all operations until HSB rises.  
2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
3. IO state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
Document Number: 001-51026 Rev. **  
Page 6 of 18  
[+] Feedback  
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