Datasheet > 存储 > SRAM> STK12C68-5C55M

STK12C68-5C55M

更新时间： 2024-01-30 22:03:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器
页数	文件大小	规格书
18页	575K
描述
64 Kbit (8K x 8) AutoStore nvSRAM

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技术参数
数据手册

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STK12C68-5C55M 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	WDIP, DIP28,.3	Reach Compliance Code：	unknown
ECCN代码：	3A001.A.2.C	HTS代码：	8542.32.00.41
风险等级：	8.66	Is Samacsys：	N
最长访问时间：	35 ns	其他特性：	RETENTION/ENDURANCE = 10 YEARS/100000 CYCLES
JESD-30 代码：	R-CDIP-T28	JESD-609代码：	e0
长度：	35.56 mm	内存密度：	65536 bit
内存集成电路类型：	NON-VOLATILE SRAM	内存宽度：	8
功能数量：	1	端口数量：	1
端子数量：	28	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	8KX8	输出特性：	3-STATE
可输出：	YES	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	WDIP	封装等效代码：	DIP28,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE, WINDOW
并行/串行：	PARALLEL	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
座面最大高度：	4.14 mm	最大待机电流：	0.004 A
子类别：	SRAMs	最大压摆率：	0.075 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	Base Number Matches：	1

STK12C68-5C55M 数据手册

STK12C68-5 (SMD5962-94599)

4. Read address 0x1FFF, Valid READ

5. Read address 0x10F0, Valid READ

6. Read address 0x0F0E, Initiate RECALL cycle

Figure 5. Current Versus Cycle Time (Read)

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared; then, the nonvolatile information is transferred into the

SRAM cells. After the t_RECALLcycle time, the SRAM is again

ready for Read and Write operations. The RECALL operation

does not alter the data in the nonvolatile elements. The nonvol-

atile data can be recalled an unlimited number of times.

Data Protection

The STK12C68-5 protects data from corruption during low

voltage conditions by inhibiting all externally initiated STORE

and Write operations. The low voltage condition is detected

when V_CCis less than V_SWITCH. If the STK12C68-5 is in a Write

mode (both CE and WE are low) at power up after a RECALL or

after a STORE, the Write is inhibited until a negative transition

on CE or WE is detected. This protects against inadvertent writes

during power up or brown out conditions.

Figure 6. Current Versus Cycle Time (Write)

Noise Considerations

The STK12C68-5 is a high speed memory. It must have a high

frequency bypass capacitor of approximately 0.1 µF connected

between V_CCand V_SS,using leads and traces that are as short

as possible. As with all high speed CMOS ICs, careful routing of

power, ground, and signals reduce circuit noise.

Hardware Protect

The STK12C68-5 offers hardware protection against inadvertent

STORE operation and SRAM Writes during low voltage condi-

tions. When V_CAP<V_SWITCH, all externally initiated STORE

operations and SRAM Writes are inhibited. AutoStore can be

completely disabled by tying VCC to ground and applying +5V to

Preventing Store

_CAP. This is the AutoStore Inhibit mode; in this mode, STOREs

are only initiated by explicit request using either the software

sequence or the HSB pin.

The STORE function is disabled by holding HSB high with a

driver capable of sourcing 30 mA at a V_OHof at least 2.2V,

because it must overpower the internal pull down device. This

device drives HSB LOW for 20 μs at the onset of a STORE.

When the STK12C68-5 is connected for AutoStore operation

Low Average Active Power

CMOS technology provides the STK12C68-5 the benefit of

drawing significantly less current when it is cycled at times longer

than 50 ns. Figure 5 and Figure 6 shows the relationship

between I_CCand Read or Write cycle time. Worst case current

consumption is shown for both CMOS and TTL input levels

(commercial temperature range, VCC = 5.5V, 100% duty cycle

on chip enable). Only standby current is drawn when the chip is

disabled. The overall average current drawn by the STK12C68-5

depends on the following items:

(system V_CCconnected to V_CCand a 68 μF capacitor on V_CAP

)

and V_CCcrosses V_SWITCHon the way down, the STK12C68-5

attempts to pull HSB LOW. If HSB does not actually get below

V_IL, the part stops trying to pull HSB LOW and abort the STORE

attempt.

■ The duty cycle of chip enable

■ The overall cycle rate for accesses

■ The ratio of Reads to Writes

■ CMOS versus TTL input levels

■ The operating temperature

■ The V_CClevel

Document Number: 001-51026 Rev. **

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与STK12C68-5C55M相关器件

型号	品牌	描述	获取价格	数据表
STK12C68-5CF25	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5CF25I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5CF25M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5CF35	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5CF35I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5CF35M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格

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