512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
FEATURES:
1
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Software Status
•
•
Single 2.7-3.6V Read and Write Operations
Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
Byte Serial Read with Single Command
2
•
•
•
•
10 MHz Max Clock Frequency
Superior Reliability
Hardware Reset Pin (RESET#)
– Resets the device to Standby Mode
CMOS I/O Compatibility
3
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
•
Low Power Consumption:
4
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
Hardware Data Protection
– Protects and unprotects the device
from Write operation
•
•
Sector or Chip-Erase Capability
– Uniform 4 KByte sectors
5
•
Packages Available
Fast Erase and Byte-Program:
– 8-Pin SOIC (4.9mm x 6mm)
– Chip-Erase Time: 70 ms (typical)
– Sector-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
6
7
PRODUCT DESCRIPTION
8
Read
The Read operation outputs the data in order from the
initialaccessedaddress.WhileSCKisinput,theaddress
will be incremented automatically until end (top) of the
address space, then the internal address pointer auto-
matically increments to beginning (bottom) of the ad-
dressspace(00000H),anddataoutstreamwillcontinue.
The read data stream is continuous through all ad-
dresses until terminated by a low to high transition on
CE#.
The SST45VF512, SST45VF010 and SST45VF020 are
manufactured with SST’s proprietary, high performance
CMOS SuperFlash technology. The Serial Flash is
organizedas16sectorsof4096BytesforSST45VF512,
32 sectors of 4096 Bytes for the SST45VF010 and
64 sectors of 4096 Bytes for the SST45VF020. The
memory is accessed for Read or Erase/Program by the
SPI bus compatible serial protocol. The bus signals are:
serialdatainput(SI), serialdataoutput(SO), serialclock
(SCK), write protect (WP#), chip enable (CE#), and
hardware reset (RESET#).
9
10
11
12
13
14
15
16
Sector/Chip-Erase Operation
TheSector-Eraseoperationclearsallbitsintheselected
sector to “FF”. The Chip-Erase instruction clears all bits
in the device to “FF”.
The SST45VFxxx devices are offered in 8-pin SOIC
package. See Figure 1 for the pinout.
Device Operation
Byte-Program Operation
The SST45VFxxx uses bus cycles of 8 bits each for
commands, data, and addresses to execute operations.
The operation instructions are listed in Table 2.
The Byte-Program operation programs the bits in the
selectedbytetothedesireddata.Theselectedbytemust
be in the erased state (“FF”) when initiating a Program
operation. The data is input from bit 7 to bit 0 in order.
All instructions are synchronized off a high to low transi-
tion of CE#. The first low to high transition on SCK will
initiate the instruction sequence. Inputs will be accepted
on the rising edge of SCK starting with the most signifi-
cantbit.AnylowtohightransitiononCE#beforetheinput
instruction completes will terminate any instruction in
progress and return the device to the standby mode.
Software Status Operation
The Status operation determines if an Erase or Program
operation is in progress. If bit 0 is at a “0” an Erase or
Programoperationisinprogress,thedeviceisbusy.Ifbit
0isata“1”thedeviceisreadyforanyvalidoperation.The
status read is continuous with ongoing clock cycles until
terminated by a low to high transition on CE#.
514-1 10/00
S71178
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered tradema1rks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
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