1 Mbit Serial Flash
SST45LF010
SST45LF0101Mb 4-wire Serial Interface flash memory
Data Sheet
FEATURES:
•
•
•
•
Single 3.0-3.6V Read and Write Operations
•
•
Automatic Write Timing
Serial Interface Architecture
Byte Serial Read with Single Command
Superior Reliability
– Internal VPP Generation
End-of-Write Detection
– Software Status
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
10 MHz Max Clock Frequency
Hardware Reset Pin (RST#)
– Resets the device to Standby Mode
CMOS I/O Compatibility
•
Low Power Consumption
– Active Current: 10 mA (typical)
– Standby Current: 10 µA (typical)
•
•
Hardware Data Protection (WP#)
•
•
Sector or Chip-Erase Capability
– Uniform 4 KByte sectors
– Protects and unprotects the device from Write
operation
Fast Erase and Byte-Program
•
Packages Available
– Chip-Erase Time: 70 ms (typical)
– Sector-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
– 8-lead SOIC (4.9mm x 6mm)
– 8-contact WSON
PRODUCT DESCRIPTION
The SST45LF010 is a 1 Mbit serial flash memory manufac-
tured with SST’s proprietary, high performance CMOS
SuperFlash technology. The 1 Mbit of memory is organized
as 32 sectors of 4096 Bytes. The flash memory uses a 4-
wire serial interface and a chip enable to select and
sequentially access its data. The serial interface consists
of; serial data input (SI), serial data output (SO), serial clock
(SCK), and chip enable (CE#). A write protect (WP#) inhib-
its the entire memory from Write operation and a hardware
reset pin (RST#) resets the device to standby mode.
Read
The Read operation outputs the data in order from the ini-
tial accessed address. While SCK is input, the address will
be incremented automatically until end (top) of the address
space (1FFFFH), then the internal address pointer auto-
matically increments to beginning (bottom) of the address
space (00000H), and data out stream will continue. The
read data stream is continuous through all addresses until
terminated by a low to high transition on CE#.
The SST45LF010 device is offered in both 8-lead SOIC
and 8-contact WSON packages. See Figure 2 for the pin
assignments.
Sector/Chip-Erase Operation
The Sector-Erase operation clears all bits in the selected
sector to FFH. The Chip-Erase instruction clears all bits in
the device to FFH.
Device Operation
The SST45LF010 uses bus cycles of 8 bits each for com-
mands, data, and addresses to execute operations. The
operation instructions are listed in Table 3.
Byte-Program Operation
The Byte-Program operation programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. The data is input from bit 7 to bit 0 in order.
All instructions are synchronized off a high to low transition
of CE#. The first low to high transition on SCK will initiate
the instruction sequence. Inputs will be accepted on the ris-
ing edge of SCK starting with the most significant bit. Any
low to high transition on CE# before the input instruction
completes will terminate any instruction in progress and
return the device to the standby mode.
Software Status Operation
The Status operation determines if an Erase or Program
operation is in progress. If bit 0 is at a “0” an Erase or Pro-
gram operation is in progress, the device is busy. If bit 0 is
at a “1” the device is ready for any valid operation. The sta-
tus read is continuous with ongoing clock cycles until termi-
nated by a low to high transition on CE#.
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71128-04-000 3/03
1
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