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SST39VF1602C-70-4C-B3KE-T PDF预览

SST39VF1602C-70-4C-B3KE-T

更新时间: 2024-11-29 15:52:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 内存集成电路闪存
页数 文件大小 规格书
39页 372K
描述
SST39VF1602C-70-4C-B3KE-T

SST39VF1602C-70-4C-B3KE-T 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:FBGA, BGA48,6X8,32Reach Compliance Code:compliant
风险等级:5.55最长访问时间:70 ns
启动块:TOP命令用户界面:YES
通用闪存接口:YES数据轮询:YES
JESD-30 代码:R-PBGA-B48内存密度:16777216 bit
内存集成电路类型:FLASH内存宽度:16
部门数/规模:1,2,1,31端子数量:48
字数:1048576 words字数代码:1000000
最高工作温度:70 °C最低工作温度:
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA48,6X8,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
并行/串行:PARALLEL电源:3/3.3 V
认证状态:Not Qualified就绪/忙碌:YES
部门规模:8K,4K,16K,32K最大待机电流:0.00002 A
子类别:Flash Memories最大压摆率:0.035 mA
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
切换位:YES类型:NOR TYPE
Base Number Matches:1

SST39VF1602C-70-4C-B3KE-T 数据手册

 浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第2页浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第3页浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第4页浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第5页浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第6页浏览型号SST39VF1602C-70-4C-B3KE-T的Datasheet PDF文件第7页 
16 Mbit (x16) Multi-Purpose Flash Plus  
SST39VF1601C / SST39VF1602C  
A Microchip Technology Company  
Data Sheet  
The SST39VF1601C / SST39VF1602C devices are 1M x16 CMOS Multi-Purpose  
Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS  
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injec-  
tor attain better reliability and manufacturability compared with alternate  
approaches. The SST39VF1601C / SST39VF1602C write (Program or Erase)  
with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pin-  
outs for x16 memories.  
Features  
• Organized as 1M x16: SST39VF1601C/1602C  
• Security-ID Feature  
– SST: 128 bits; User: 128 words  
• Single Voltage Read and Write Operations  
• Fast Read Access Time:  
– 2.7-3.6V  
– 70 ns  
• Superior Reliability  
• Fast Erase and Word-Program:  
– Endurance: 100,000 Cycles (Typical)  
– Greater than 100 years Data Retention  
– Sector-Erase Time: 18 ms (typical)  
– Block-Erase Time: 18 ms (typical)  
– Chip-Erase Time: 40 ms (typical)  
– Word-Program Time: 7 µs (typical)  
• Low Power Consumption (typical values at 5 MHz)  
– Active Current: 9 mA (typical)  
– Standby Current: 3 µA (typical)  
– Auto Low Power Mode: 3 µA (typical)  
• Automatic Write Timing  
– Internal VPP Generation  
• Hardware Block-Protection/WP# Input Pin  
• End-of-Write Detection  
– Top Block-Protection (top 8 KWord)  
– Bottom Block-Protection (bottom 8 KWord)  
– Toggle Bits  
– Data# Polling  
– Ready/Busy# Pin  
• Sector-Erase Capability  
– Uniform 2 KWord sectors  
• CMOS I/O Compatibility  
• Block-Erase Capability  
• JEDEC Standard  
– Flexible block architecture; one 8-, two 4-, one 16-, and  
thirty one 32-KWord blocks  
– Flash EEPROM Pinouts and command sets  
• Chip-Erase Capability  
• Packages Available  
– 48-lead TSOP (12mm x 20mm)  
– 48-ball TFBGA (6mm x 8mm)  
– 48-ball WFBGA (4mm x 6mm)  
• Erase-Suspend/Erase-Resume Capabilities  
• Hardware Reset Pin (RST#)  
• Latched Address and Data  
• All devices are RoHS compliant  
www.microchip.com  
©2011 Silicon Storage Technology, Inc.  
DS-25018A  
05/11  

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