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SST39VF080-90-4C-B2K PDF预览

SST39VF080-90-4C-B2K

更新时间: 2024-11-25 23:34:31
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其他 - ETC 闪存内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 251K
描述
x8 Flash EEPROM

SST39VF080-90-4C-B2K 数据手册

 浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第2页浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第3页浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第4页浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第5页浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第6页浏览型号SST39VF080-90-4C-B2K的Datasheet PDF文件第7页 
8 Mbit / 16 Mbit (x8) Multi-Purpose Flash  
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016  
Data Sheet  
FEATURES:  
Organized as 1M x8 / 2M x8  
Fast Erase and Byte-Program:  
1
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-
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-
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Sector-Erase Time: 18 ms (typical)  
Block-Erase Time: 18 ms (typical)  
Chip-Erase Time: 70 ms (typical)  
Byte-Program Time: 14 µs (typical)  
Chip Rewrite Time:  
15 seconds (typical) for SST39LF/VF080  
30 seconds (typical) for SST39LF/VF016  
Single Voltage Read and Write Operations  
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3.0-3.6V for SST39LF080/016  
2.7-3.6V for SST39VF080/016  
2
Superior Reliability  
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Endurance: 100,000 Cycles (typical)  
Greater than 100 years Data Retention  
3
Low Power Consumption:  
Automatic Write Timing  
Internal VPP Generation  
End-of-Write Detection  
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-
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Active Current: 15 mA (typical)  
Standby Current: 4 µA (typical)  
Auto Low Power Mode: 4 µA (typical)  
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4
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Toggle Bit  
Data# Polling  
Sector-Erase Capability  
Uniform 4 KByte sectors  
Block-Erase Capability  
Uniform 64 KByte blocks  
Fast Read Access Time:  
-
CMOS I/O Compatibility  
5
JEDEC Standard  
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-
Flash EEPROM Pinouts and command sets  
6
Packages Available  
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55 ns for SST39LF080/016  
70 and 90 ns for SST39VF080/016  
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40-Pin TSOP (10mm x 20mm)  
48-Ball TFBGA (6mm x 8mm)  
7
Latched Address and Data  
PRODUCT DESCRIPTION  
Erase and Program than alternative flash technologies.  
The total energy consumed is a function of the applied  
voltage, current, and time of application. Since for any  
givenvoltagerange,theSuperFlashtechnologyusesless  
current to program and has a shorter erase time, the total  
energyconsumedduringanyEraseorProgramoperation  
is less than alternative flash technologies. They also  
improveflexibilitywhileloweringthecostforprogram,data,  
and configuration storage applications.  
8
TheSST39LF/VF080andSST39LF/VF016devicesare  
1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF)  
manufacturedwithSST’sproprietary,highperformance  
CMOS SuperFlash technology. The split-gate cell de-  
sign and thick oxide tunneling injector attain better  
reliabilityandmanufacturabilitycomparedwithalternate  
approaches. The SST39LF080/016 write (Program or  
Erase) with a 3.0-3.6V power supply. The  
SST39VF080/016 write (Program or Erase) with a 2.7-  
3.6V power supply. They conform to JEDEC standard  
pinouts for x8 memories.  
9
10  
11  
12  
13  
14  
15  
16  
The SuperFlash technology provides fixed Erase and  
Program times, independent of the number of Erase/  
Program cycles that have occurred. Therefore the sys-  
tem software or hardware does not have to be modified  
or de-rated as is necessary with alternative flash tech-  
nologies, whose Erase and Program times increase  
with accumulated Erase/Program cycles.  
Featuring high performance Byte-Program, the  
SST39LF/VF080andSST39LF/VF016devicesprovide  
atypicalByte-Programtimeof14µsec.Thedevicesuse  
Toggle Bit or Data# Polling to indicate the completion of  
Programoperation.Toprotectagainstinadvertentwrite,  
they have on-chip hardware and Software Data Protec-  
tion schemes. Designed, manufactured, and tested for  
a wide spectrum of applications, these devices are  
offered with a guaranteed endurance of 10,000 cycles.  
Data retention is rated at greater than 100 years.  
To meet high density, surface mount requirements, the  
SST39LF/VF080 and SST39LF/VF016 are offered in  
40-pin TSOP and 48-ball TFBGA packaging. See  
Figures 1 and 2 for pinouts.  
Device Operation  
Commands are used to initiate the memory operation  
functions of the device. Commands are written to the  
device using standard microprocessor write se-  
quences. A command is written by asserting WE# low  
while keeping CE# low. The address bus is latched on  
the falling edge of WE# or CE#, whichever occurs last.  
The data bus is latched on the rising edge of WE# or  
CE#, whichever occurs first.  
The SST39LF/VF080 and SST39LF/VF016 devices are  
suited for applications that require convenient and eco-  
nomical updating of program, configuration, or data  
memory. For all system applications, they significantly  
improve performance and reliability, while lowering power  
consumption. They inherently use less energy during  
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.  
396-2 11/00 S71146 These specifications are subject to change without notice.  

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