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SST37VF010-90-3C-NHE PDF预览

SST37VF010-90-3C-NHE

更新时间： 2024-11-23 15:52:55
品牌 Logo 应用领域
芯科 - SILICON 内存集成电路
页数 文件大小 规格书
17页 185K
描述
Flash, 128KX8, 90ns, PQCC32, PLASTIC, MS-016AE, LCC-32

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SST37VF010-90-3C-NHE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：QFJ
包装说明：PLASTIC, MS-016AE, LCC-32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.47
最长访问时间：90 ns命令用户界面：NO
数据轮询：NOJESD-30 代码：R-PQCC-J32
JESD-609代码：e3长度：13.97 mm
内存密度：1048576 bit内存集成电路类型：FLASH
内存宽度：8功能数量：1
端子数量：32字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3/3.3 V编程电压：2.7 V
认证状态：Not Qualified座面最大高度：3.556 mm
最大待机电流：0.000015 A子类别：Flash Memories
最大压摆率：0.02 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
切换位：NO类型：NOR TYPE
宽度：11.43 mmBase Number Matches：1

SST37VF010-90-3C-NHE 数据手册

 浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第2页浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第3页浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第4页浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第5页浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第6页浏览型号SST37VF010-90-3C-NHE的Datasheet PDF文件第7页 
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)  
Many-Time Programmable Flash  
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040  
SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories  
Data Sheet  
FEATURES:  
•
•
•
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8  
2.7-3.6V Read Operation  
•
•
Fast Byte-Program Operation:  
– Byte-Program Time: 10 µs (typical)  
– Chip Program Time:  
Superior Reliability  
0.6 seconds (typical) for SST37VF512  
1.2 seconds (typical) for SST37VF010  
2.4 seconds (typical) for SST37VF020  
4.8 seconds (typical) for SST37VF040  
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
•
•
•
Low Power Consumption:  
– Active Current: 10 mA (typical)  
– Standby Current: 2 µA (typical)  
Electrical Erase Using Programmer  
– Does not require UV source  
– Chip-Erase Time: 100 ms (typical)  
Fast Read Access Time:  
– 70 ns  
– 90 ns  
•
•
CMOS I/O Compatibility  
JEDEC Standard Byte-wide Flash  
EEPROM Pinouts  
Latched Address and Data  
•
Packages Available  
– 32-lead PLCC  
– 32-lead TSOP (8mm x 14mm)  
– 32-pin PDIP  
PRODUCT DESCRIPTION  
The SST37VF512/010/020/040 devices are 64K x8 / 128K  
x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable  
(MTP), low cost flash, manufactured with SST’s proprietary,  
high performance CMOS SuperFlash technology. The  
split-gate cell design and thick-oxide tunneling injector  
attain better reliability and manufacturability compared with  
alternate approaches. The SST37VF512/010/020/040 can  
be electrically erased and programmed at least 1000 times  
using an external programmer, e.g., to change the contents  
of devices in inventory. The SST37VF512/010/020/040  
have to be erased prior to programming. These devices  
conform to JEDEC standard pinouts for byte-wide flash  
memories.  
To meet surface mount and conventional through hole  
requirements, the SST37VF512/010/020/040 are offered in  
32-lead PLCC, 32-lead TSOP, and 32-pin PDIP packages.  
See Figures 1, 2, and 3 for pin assignments.  
Device Operation  
The SST37VF512/010/020/040 devices are nonvolatile  
memory solutions that can be used instead of standard  
flash devices if in-system programmability is not required. It  
is functionally (Read) and pin compatible with industry  
standard flash products.The device supports electrical  
Erase operation via an external programmer.  
Featuring high performance Byte-Program, the  
SST37VF512/010/020/040 provide a typical Byte-Pro-  
gram time of 10 µs. Designed, manufactured, and tested  
for a wide spectrum of applications, these devices are  
offered with an endurance of at least 1000 cycles. Data  
retention is rated at greater than 100 years.  
Read  
The Read operation of the SST37VF512/010/020/040 is  
controlled by CE# and OE#. Both CE# and OE# have to be  
low for the system to obtain data from the outputs. Once  
the address is stable, the address access time is equal to  
the delay from CE# to output (TCE). Data is available at the  
output after a delay of TOE from the falling edge of OE#,  
assuming the CE# pin has been low and the addresses  
have been stable for at least TCE-TOE. When the CE# pin is  
high, the chip is deselected and a standby current of only  
10 µA (typical) is consumed. OE# is the output control and  
is used to gate data from the output pins. The data bus is in  
high impedance state when either CE# or OE# is VIH. Refer  
to Figure 4 for the timing diagram.  
The SST37VF512/010/020/040 are suited for applications  
that require infrequent writes and low power nonvolatile  
storage. These devices will improve flexibility, efficiency,  
and performance while matching the low cost in nonvolatile  
applications that currently use UV-EPROMs, OTPs, and  
mask ROMs.  
©2003 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MTP is a trademark of Silicon Storage Technology, Inc.  
S71151-04-000 11/03  
1
397  
These specifications are subject to change without notice.  
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