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SST37VF020-70-3I-WH PDF预览

SST37VF020-70-3I-WH

更新时间: 2024-11-25 23:34:31
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页数 文件大小 规格书
16页 188K
描述
x8 Flash EEPROM

SST37VF020-70-3I-WH 数据手册

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)  
Many-Time Programmable Flash  
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040  
Data Sheet  
FEATURES:  
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8  
Fast Byte-Program Operation  
– Byte-Program Time: 10 µs (typical)  
– Chip-Program Time:  
2.7-3.6V Read Operation  
Superior Reliability  
1
0.6 seconds (typical) for SST37VF512  
1.2 seconds (typical) for SST37VF010  
2.4 seconds (typical) for SST37VF020  
4.8 seconds (typical) for SST37VF040  
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
2
Low Power Consumption  
Electrical Erase Using Programmer  
– Active Current: 10 mA (typical)  
– Standby Current: 1 µA (typical)  
– Does not require UV source  
– Chip-Erase Time: 100 ms (typical)  
3
Fast Read Access Time  
CMOS I/O Compatibility  
– 70 and 90 ns  
4
JEDEC Standard Byte-wide Flash EEPROM  
Pinouts  
Packages Available  
5
– 32-Pin PDIP  
– 32-Pin PLCC  
– 32-Pin TSOP (8mm x 14mm)  
6
PRODUCT DESCRIPTION  
Device Operation  
7
The SST37VF512/010/020/040 devices are nonvolatile  
memory solutions that can be used instead of standard  
flash devices if in-system programmability is not re-  
quired. It is functionally (Read) and pin compatible with  
industry standard flash products.The device supports  
electrical Erase operation via an external programmer.  
The SST37VF512/010/020/040 devices are 64K x8 /  
128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Pro-  
grammable (MTP), low cost flash, manufactured with  
SST’s proprietary, high performance CMOS SuperFlash  
technology. The split-gate cell design and thick oxide  
tunneling injector attain better reliability and  
manufacturability compared with alternate approaches.  
TheSST37VF512/010/020/040canbeelectricallyerased  
and programmed at least 1000 times using an external  
programmer, e.g., to change the contents of devices in  
inventory. The SST37VF512/010/020/040 have to be  
erased prior to programming. These devices conform to  
JEDEC standard pinouts for byte-wide flash memories.  
8
9
Read  
The Read operation of the SST37VF512/010/020/040 is  
controlledbyCE#andOE#.BothCE#andOE#havetobe  
lowforthesystemtoobtaindatafromtheoutputs.Oncethe  
address is stable, the address access time is equal to the  
delay from CE# to output (TCE). Data is available at the  
output after a delay of TOE from the falling edge of OE#,  
assuming the CE# pin has been low and the addresses  
have been stable for at least TCE - TOE. When the CE# pin  
ishigh,thechipisdeselectedandastandbycurrentofonly  
10µA(typical)isconsumed. OE#istheoutputcontroland  
is used to gate data from the output pins. The data bus is  
in high impedance state when either CE# or OE# is VIH.  
Refer to Figure 4 for the timing diagram.  
10  
11  
12  
13  
14  
15  
16  
Featuring high performance Byte-Program, the  
SST37VF512/010/020/040 provide a typical Byte-Pro-  
gramtimeof10µs. Designed, manufactured, andtested  
for a wide spectrum of applications, these devices are  
offered with an endurance of at least 1000 cycles. Data  
retention is rated at greater than 100 years.  
The SST37VF512/010/020/040 are suited for  
applications that require infrequent writes and low  
power nonvolatile storage. These devices will  
improve flexibility, efficiency, and performance while  
matching the low cost in nonvolatile applications that  
currently use UV-EPROMs, OTPs, and mask ROMs.  
Byte-Program Operation  
The SST37VF512/010/020/040 are programmed by us-  
ing an external programmer. The programming mode is  
activated by asserting 12V (±5%) on OE# pin and VIL on  
CE#pin. Thedeviceisprogrammedusingasinglepulse  
(WE#pinlow)of10µsperbyte.UsingtheMTPprogram-  
ming algorithm, the Byte-Program process continues  
byte-by-byteuntiltheentirechiphasbeenprogrammed.  
Refer to Figure 10 for the flowchart and Figure 6 for the  
timing diagram.  
To meet surface mount and conventional through hole  
requirements, the SST37VF512/010/020/040 are of-  
fered in 32-pin PLCC, PDIP and TSOP packages. See  
Figures 1, 2 and 3 for pinouts.  
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc.  
397-03 2/00  
These specifications are subject to change without notice.  
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