Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281
SST32HF1621C / SST32HF1641C / SST32HF3241C
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
Preliminary Specifications
(x16) MCP ComboMemories
FEATURES:
•
ComboMemories organized as:
•
•
•
Security-ID Feature
– SST32HF1621C: 1M x16 Flash + 128K x16 SRAM
– SST32HF1641x: 1M x16 Flash + 256K x16 SRAM
– SST32HF1681: 1M x16 Flash + 256K x16 SRAM
– SST32HF3241x: 2M x16 Flash + 256K x16 SRAM
– SST32HF3281: 2M x16 Flash + 512K x16 SRAM
– SST: 128 bits; User: 128 bits
Hardware Block-Protection/WP# Input Pin
– Bottom Block-Protection (bottom 32 KWord)
Fast Read Access Times:
– Flash: 70 ns
– SRAM: 70 ns
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– Read from or Write to SRAM while
Erase/Program Flash
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
•
•
Flash Automatic Erase and Program Timing
– Internal VPP Generation
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current:
Flash End-of-Write Detection
- SST32HFx1: 60 µA (typical)
- SST32HFx1C: 12 µA (typical)
– Toggle Bit
– Data# Polling
•
•
Flexible Erase Capability
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
Erase-Suspend/Erase-Resume Capabilities
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HFx1/x1C ComboMemory devices integrate
a CMOS flash memory bank with a CMOS SRAM mem-
ory bank in a Multi-Chip Package (MCP), manufactured
with SST’s proprietary, high performance SuperFlash
technology. The SST32HF16x1/32x1 devices use a
PseudoSRAM. The SST32HF16x1C/32x1C devices use
standard SRAM.
signals. The SRAM bank enable signal, BES# selects the
SRAM bank. The flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HFx1/x1C devices contain on-chip hardware and
software data protection schemes. The SST32HFx1/x1C
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HFx1/x1C provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HFx1/x1C devices consist of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
©2005 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71236-04-000
1
5/05
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