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SST32HF162-70-4E-TBK PDF预览

SST32HF162-70-4E-TBK

更新时间: 2024-11-14 22:11:51
品牌 Logo 应用领域
SST 闪存静态存储器
页数 文件大小 规格书
28页 339K
描述
Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF162-70-4E-TBK 数据手册

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Multi-Purpose Flash (MPF) + SRAM ComboMemory  
SST32HF802 / SST32HF162 / SST32HF164  
SST32HF802 / 162 / 164MPF (x16) + 1Mb SRAM (x16) ComboMemories  
Data Sheet  
FEATURES:  
MPF + SRAM ComboMemory  
Latched Address and Data for Flash  
Flash Fast Erase and Word-Program:  
– SST32HF802: 512K x16 Flash + 128K x16 SRAM  
– SST32HF162: 1M x16 Flash + 128K x16 SRAM  
– SST32HF164: 1M x16 Flash + 256K x16 SRAM  
– Sector-Erase Time: 18 ms (typical)  
– Block-Erase Time: 18 ms (typical)  
– Chip-Erase Time: 70 ms (typical)  
– Word-Program Time: 14 µs (typical)  
– Chip Rewrite Time:  
Single 2.7-3.3V Read and Write Operations  
Concurrent Operation  
– Read from or write to SRAM while  
Erase/Program Flash  
SST32HF802: 8 seconds (typical)  
SST32HF162/164: 15 seconds (typical)  
Flash Automatic Erase and Program Timing  
– Internal VPP Generation  
Superior Reliability  
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
Flash End-of-Write Detection  
Low Power Consumption:  
Toggle Bit  
– Data# Polling  
– Active Current: 15 mA (typical) for  
Flash or SRAM Read  
– Standby Current: 20 µA (typical)  
CMOS I/O Compatibility  
JEDEC Standard Command Set  
Package Available  
Flexible Erase Capability  
– Uniform 2 KWord sectors  
– Uniform 32 KWord size blocks  
– 48-lead TSOP (12mm x 20mm)  
– 48-ball TBGA (10mm x 12mm)  
Fast Read Access Times:  
– Flash: 70 ns and 90 ns  
– SRAM: 70 ns and 90 ns  
bank enable signal, BEF# selects the flash memory bank.  
The WE# signal has to be used with Software Data Protec-  
tion (SDP) command sequence when controlling the Erase  
and Program operations in the flash memory bank. The  
SDP command sequence protects the data stored in the  
flash memory bank from accidental alteration.  
PRODUCT DESCRIPTION  
The SST32HF802/162/164 ComboMemory devices inte-  
grate a 512K x16 or 1M x16 CMOS flash memory bank  
with a 128K x16 or 256K x16 CMOS SRAM memory bank  
in a Multi-Chip Package (MCP), manufactured with SST’s  
proprietary, high performance SuperFlash technology.  
The SST32HF802/162/164 provide the added functionality  
of being able to simultaneously read from or write to the  
SRAM bank while erasing or programming in the flash  
memory bank. The SRAM memory bank can be read or  
written while the flash memory bank performs Sector-  
Erase, Bank-Erase, or Word-Program concurrently. All  
flash memory Erase and Program operations will automati-  
cally latch the input address and data signals and complete  
the operation in background without further input stimulus  
requirement. Once the internally controlled erase or pro-  
gram cycle in the flash bank has commenced, the SRAM  
bank can be accessed for read or write.  
Featuring high performance Word-Program, the flash  
memory bank provides a maximum Word-Program time of  
14 µsec. The entire flash memory bank can be erased and  
programmed word-by-word in typically 8 seconds for the  
SST32HF802 and 15 seconds for the SST32HF162/164,  
when using interface features such as Toggle Bit or Data#  
Polling to indicate the completion of Program operation. To  
protect against inadvertent flash write, the SST32HF802/  
162/164 devices contain on-chip hardware and software  
data protection schemes.The SST32HF802/162/164  
devices offer a guaranteed endurance of 10,000 cycles.  
Data retention is rated at greater than 100 years.  
The SST32HF802/162/164 devices are suited for applica-  
tions that use both flash memory and SRAM memory to  
store code or data. For systems requiring low power and  
small form factor, the SST32HF802/162/164 devices signif-  
icantly improve performance and reliability, while lowering  
power consumption, when compared with multiple chip  
solutions. The SST32HF802/162/164 inherently use less  
energy during erase and program than alternative flash  
The SST32HF802/162/164 devices consist of two inde-  
pendent memory banks with respective bank enable sig-  
nals. The Flash and SRAM memory banks are  
superimposed in the same memory address space. Both  
memory banks share common address lines, data lines,  
WE# and OE#. The memory bank selection is done by  
memory bank enable signals. The SRAM bank enable sig-  
nal, BES# selects the SRAM bank. The flash memory  
©2001 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71171-05-000 8/01  
1
520  

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