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SST32HF162C-70-4E-LBKE PDF预览

SST32HF162C-70-4E-LBKE

更新时间: 2024-11-15 19:56:31
品牌 Logo 应用领域
芯科 - SILICON 内存集成电路
页数 文件大小 规格书
28页 395K
描述
Memory Circuit, 1MX16, CMOS, PBGA48, 10 X 12 MM, 1.40 MM HEIGHT, MO-210, LBGA-48

SST32HF162C-70-4E-LBKE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:LBGA,
针数:48Reach Compliance Code:unknown
HTS代码:8542.32.00.71风险等级:5.84
其他特性:STATIC RAM IS ORGANIZED AS 128K X 16JESD-30 代码:R-PBGA-B48
JESD-609代码:e1长度:12 mm
内存密度:16777216 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:16功能数量:1
端子数量:48字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-20 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.4 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:24
宽度:10 mmBase Number Matches:1

SST32HF162C-70-4E-LBKE 数据手册

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Multi-Purpose Flash Plus + SRAM ComboMemory  
SST32HF162C / SST32HF164C / SST32HF324C  
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM  
Preliminary Specifications  
(x16) MCP ComboMemories  
FEATURES:  
ComboMemories organized as:  
Erase-Suspend/Erase-Resume Capabilities  
Fast Read Access Times:  
– Flash: 70 ns  
– SRAM: 70 ns  
– SST32HF162C: 1M x16 Flash + 128K x16 SRAM  
– SST32HF164C: 1M x16 Flash + 256K x16 SRAM  
– SST32HF324C: 2M x16 Flash + 256K x16 SRAM  
Single 2.7-3.3V Read and Write Operations  
Concurrent Operation  
Latched Address and Data for Flash  
Flash Fast Erase and Word-Program:  
– Read from or Write to SRAM while  
Erase/Program Flash  
Superior Reliability  
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
Low Power Consumption:  
– Active Current: 15 mA (typical) for  
Flash or SRAM Read  
– Standby Current:  
- SST32HFx1C: 12 µA (typical)  
Flexible Erase Capability  
– Sector-Erase Time: 18 ms (typical)  
– Block-Erase Time: 18 ms (typical)  
– Chip-Erase Time: 40 ms (typical)  
– Word-Program Time: 7 µs (typical)  
Flash Automatic Erase and Program Timing  
– Internal VPP Generation  
Flash End-of-Write Detection  
Toggle Bit  
– Data# Polling  
CMOS I/O Compatibility  
JEDEC Standard Command Set  
Package Available  
– Uniform 2 KWord sectors  
– Uniform 32 KWord size blocks  
– 48-ball LBGA (10mm x 12mm x 1.4mm)  
PRODUCT DESCRIPTION  
The SST32HF16xC/324C ComboMemory devices inte-  
grate a CMOS flash memory bank with a CMOS SRAM  
memory bank in a Multi-Chip Package (MCP), manufac-  
tured with SST’s proprietary, high performance Super-  
Flash technology.  
selects the SRAM bank. The flash memory bank enable  
signal, BEF# selects the flash memory bank. The WE# sig-  
nal has to be used with Software Data Protection (SDP)  
command sequence when controlling the Erase and Pro-  
gram operations in the flash memory bank. The SDP com-  
mand sequence protects the data stored in the flash  
memory bank from accidental alteration.  
Featuring high performance Word-Program, the flash  
memory bank provides a maximum Word-Program time of  
7 µsec. To protect against inadvertent flash write, the  
SST32HF16xC/324C devices contain on-chip hardware  
and software data protection schemes. The  
SST32HF16xC/324C devices offer a guaranteed endur-  
ance of 10,000 cycles. Data retention is rated at greater  
than 100 years.  
The SST32HF16xC/324C provide the added functionality  
of being able to simultaneously read from or write to the  
SRAM bank while erasing or programming in the flash  
memory bank. The SRAM memory bank can be read or  
written while the flash memory bank performs Sector-  
Erase, Bank-Erase, or Word-Program concurrently. All  
flash memory Erase and Program operations will automati-  
cally latch the input address and data signals and complete  
the operation in background without further input stimulus  
requirement. Once the internally controlled Erase or Pro-  
gram cycle in the flash bank has commenced, the SRAM  
bank can be accessed for Read or Write.  
The SST32HF16xC/324C devices consist of two indepen-  
dent memory banks with respective bank enable signals.  
The Flash and SRAM memory banks are superimposed in  
the same memory address space. Both memory banks  
share common address lines, data lines, WE# and OE#.  
The memory bank selection is done by memory bank  
enable signals. The SRAM bank enable signal, BES#  
©2004 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71267-00-000  
1
7/04  

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