Datasheet > SST31LH021-70-4I-WI

SST31LH021-70-4I-WI

更新时间： 2024-11-15 20:11:31

品牌	Logo	应用领域
芯科 - SILICON		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
24页	239K
描述
Memory Circuit, Flash+SRAM, CMOS, PDSO40

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SST31LH021-70-4I-WI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	TSSOP, TSSOP40,.56,20	Reach Compliance Code：	unknown
风险等级：	5.92	最长访问时间：	70 ns
JESD-30 代码：	R-PDSO-G40	JESD-609代码：	e0
内存集成电路类型：	MEMORY CIRCUIT	混合内存类型：	FLASH+SRAM
端子数量：	40	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP40,.56,20
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
最大待机电流：	0.00003 A	子类别：	Other Memory ICs
最大压摆率：	0.035 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	DUAL	Base Number Matches：	1

SST31LH021-70-4I-WI 数据手册

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2 Megabit Flash + 1 Megabit SRAM ComboMemory

SST31LH021

Advance Information

FEATURES:

•

Organized as 256K x8 flash + 128K x8 SRAM

Single 3.0-3.6V Read and Write Operations

Concurrent Operation

•

Latched Address and Data for Flash

Flash Fast Sector-Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Bank-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Bank Rewrite Time: 4 seconds (typical)

– Read from or Write to SRAM while

Erase/Program Flash

•

Superior Reliability

•

Flash Automatic Erase and Program Timing

– Internal V_PPGeneration

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

Flash End of Write Detection

Low Power Consumption:

– Toggle Bit

– Data# Polling

– Active Current: 10 mA (typical) for Flash

and 20 mA (typical) for SRAM Read

– Standby Current: 700 µA (typical)

•

CMOS I/O Compatibility

JEDEC Standard Command Set

Packages Available

•

Sector-Erase Capability

– Uniform 4 KByte sectors

Fast Read Access Times:

– 32-Pin TSOP (8mm x 14mm)

– 40-Pin TSOP (10mm x 14mm)

– Flash: 70 ns

– SRAM: 25 ns

PRODUCT DESCRIPTION

signal, BEF# selects the flash memory bank. The WE#

signal has to be used with Software Data Protection

(SDP) command sequence when controlling the Erase

and Program operations in the flash memory bank. The

SDPcommandsequenceprotectsthedatastoredinthe

flash memory bank from accidental alteration.

The SST31LH021 is a 256K x8 CMOS flash memory

bank combined with a 128K x8 CMOS SRAM memory

bank manufactured with SST’s proprietary, high perfor-

mance SuperFlash technology. The SST31LH021 de-

vice writes (SRAM or flash) with a 3.0-3.6V power

supply.ThemonolithicSST31LH021deviceconformsto

JEDEC standard pinouts and Software Data Protect

(SDP) commands for x8 EEPROMs in TSOP packages.

The SST31LH021 provides the added functionality of

being able to simultaneously read from or write to the

SRAM bank while erasing or programming in the flash

memory bank. The SRAM memory bank can be read or

written while the flash memory bank performs Sector-

Erase, Bank-Erase, or Byte-Program concurrently. All

flash memory Erase and Program operations will auto-

matically latch the input address and data signals and

complete the operation in background without further

input stimulus requirement. Once the internally con-

trolled Erase or Program cycle in the flash bank has

commenced,theSRAMbankcanbeaccessedforRead

or Write.

Featuring high performance Byte-Program, the flash

memory bank provides a maximum Byte-Program time

of 20 µsec. The entire flash memory bank can be erased

and programmed byte-by-byte in typically 4 seconds,

when using interface features such as Toggle Bit or

Data# Polling to indicate the completion of Program

operation. To protect against inadvertent flash write, the

SST31LH021 device has on-chip hardware and soft-

ware data protection schemes. Designed, manufac-

tured,andtestedforawidespectrumofapplications,the

SST31LH021deviceisofferedwithaguaranteedendur-

ance of 10,000 cycles. Data retention is rated at greater

than 100 years.

The SST31LH021 device is suited for applications that

use both nonvolatile flash memory and volatile SRAM

memory to store code or data. For all system applica-

tions, the SST31LH021 device significantly improves

performance and reliability, while lowering power con-

sumption, when compared with multiple chip solutions.

The SST31LH021 inherently uses less energy during

Erase and Program than alternative flash technologies.

When programming a flash device, the total energy

consumed is a function of the applied voltage, current,

and time of application. Since for any given voltage

TheSST31LH021operatesastwoindependentmemory

banks with respective bank enable signals. The SRAM

andFlashmemorybanksaresuperimposedinthesame

memory address space. Both memory banks share

common address lines, data lines, WE# and OE#. The

memory bank selection is done by memory bank enable

signals. The SRAM bank enable signal, BES# selects

the SRAM bank and the flash memory bank enable

353-11 11/99

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与SST31LH021-70-4I-WI相关器件

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