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SST27SF020-70-3C-PHE PDF预览

SST27SF020-70-3C-PHE

更新时间: 2024-11-01 04:30:43
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描述
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

SST27SF020-70-3C-PHE 数据手册

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512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash  
SST27SF512 / SST27SF010 / SST27SF020  
SST27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories  
Data Sheet  
FEATURES:  
Organized as 64K x8 / 128K x8 / 256K x8  
4.5-5.5V Read Operation  
Fast Byte-Program Operation  
– Byte-Program Time: 20 µs (typical)  
– Chip Program Time:  
Superior Reliability  
1.4 seconds (typical) for SST27SF512  
2.8 seconds (typical) for SST27SF010  
5.6 seconds (typical) for SST27SF020  
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
Low Power Consumption  
Electrical Erase Using Programmer  
– Active Current: 20 mA (typical)  
– Standby Current: 10 µA (typical)  
– Does not require UV source  
– Chip-Erase Time: 100 ms (typical)  
Fast Read Access Time  
TTL I/O Compatibility  
– 70 ns  
JEDEC Standard Byte-wide EPROM Pinouts  
Packages Available  
– 32-lead PLCC  
– 32-lead TSOP (8mm x 14mm)  
– 28-pin PDIP for SST27SF512  
– 32-pin PDIP for SST27SF010/020  
All non-Pb (lead-free) devices are RoHS compliant  
PRODUCT DESCRIPTION  
The SST27SF512/010/020 are a 64K x8 / 128K x8 / 256K  
x8 CMOS, Many-Time Programmable (MTP) low cost  
flash, manufactured with SST’s proprietary, high perfor-  
mance SuperFlash technology. The split-gate cell design  
and thick oxide tunneling injector attain better reliability and  
manufacturability compared with alternate approaches.  
These MTP devices can be electrically erased and pro-  
grammed at least 1000 times using an external program-  
mer with a 12V power supply. They have to be erased prior  
to programming. These devices conform to JEDEC stan-  
dard pinouts for byte-wide memories.  
Device Operation  
The SST27SF512/010/020 are a low cost flash solution  
that can be used to replace existing UV-EPROM, OTP,  
and mask ROM sockets. These devices are functionally  
(read and program) and pin compatible with industry  
standard EPROM products. In addition to EPROM func-  
tionality, these devices also support electrical Erase  
operation via an external programmer. They do not  
require a UV source to erase, and therefore the pack-  
ages do not have a window.  
Featuring  
high-performance  
Byte-Program,  
the  
Read  
SST27SF512/010/020 provide a Byte-Program time of 20  
µs. Designed, manufactured, and tested for a wide spec-  
trum of applications, these devices are offered with an  
endurance of at least 1000 cycles. Data retention is rated at  
greater than 100 years.  
The Read operation of the SST27SF512/010/020 is con-  
trolled by CE# and OE#. Both CE# and OE# have to be low  
for the system to obtain data from the outputs. Once the  
address is stable, the address access time is equal to the  
delay from CE# to output (TCE). Data is available at the out-  
put after a delay of TOE from the falling edge of OE#,  
assuming that CE# pin has been low and the addresses  
have been stable for at least TCE-TOE. When the CE# pin is  
high, the chip is deselected and a typical standby current of  
10 µA is consumed. OE# is the output control and is used  
to gate data from the output pins. The data bus is in high  
impedance state when either CE# or OE# is high.  
The SST27SF512/010/020 are suited for applications that  
require infrequent writes and low power nonvolatile stor-  
age. These devices will improve flexibility, efficiency, and  
performance while matching the low cost in nonvolatile  
applications that currently use UV-EPROMs, OTPs, and  
mask ROMs.  
To meet surface mount and conventional through hole  
requirements, the SST27SF512 are offered in 32-lead  
PLCC, 32-lead TSOP, and 28-pin PDIP packages. The  
SST27SF010/020 are offered in 32-pin PDIP, 32-lead  
PLCC, and 32-lead TSOP packages. See Figures 1, 2, and  
3 for pin assignments.  
©2005 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MTP is a trademark of Silicon Storage Technology, Inc.  
S71152-11-000  
1
9/05  
These specifications are subject to change without notice.  

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