Datasheet > SPC5643LAMLQ1

SPC5643LAMLQ1

更新时间： 2024-10-29 15:17:15

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
136页	1175K
描述
NXP 32-bit MCU, Dual Power Arch, 1MB Flash, 120MHz, -40/+125degC, Automotive Grade, QFP 144

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SPC5643LAMLQ1 数据手册

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5643L

Rev. 10, 11/2021

MPC5643L

MAPBGA–225

QFN12

15 mm x 15 mm

##_mm_x_##mm

SOT-343R

##_mm_x_##mm

144 LQFP

PKG-TBD

MPC5643L Microcontroller

Data Sheet

## mm x ## mm

TBD

257 MAPBGA

(20 x 20 x 1.4 mm)

(14 x 14 x 0.8 mm)

—

Cyclic redundancy check (CRC) unit

•

High-performance e200z4d dual core

•

Decoupled Parallel mode for high-performance use of

replicated cores

Nexus Class 3+ interface

Interrupts

—

GPIOs individually programmable as input, output or

special function

Three 6-channel general-purpose eTimer units

2 FlexPWM units

—

32-bit Power Architecture^®technology CPU

Core frequency as high as 120 MHz

Dual issue five-stage pipeline core

Variable Length Encoding (VLE)

Memory Management Unit (MMU)

4 KB instruction cache with error detection code

Signal processing engine (SPE)

•

Replicated 16-priority controller

Replicated 16-channel eDMA controller

•

Memory available

•

—

1 MB flash memory with ECC

128 KB on-chip SRAM with ECC

Built-in RWW capabilities for EEPROM emulation

—

Four 16-bit channels per module

•

Communications interfaces

—

SIL3/ASILD innovative safety concept: LockStep mode and

Fail-safe protection

2 LINFlexD channels

3 DSPI channels with automatic chip select

generation

2 FlexCAN interfaces (2.0B Active) with 32

message objects

FlexRay module (V2.1 Rev. A) with 2 channels,

64 message buffers and data rates up to 10 Mbit/s

—

Sphere of replication (SoR) for key components (such as

CPU core, eDMA, crossbar switch)

—

Fault collection and control unit (FCCU)

Redundancy control and checker unit (RCCU) on outputs

of the SoR connected to FCCU

—

Boot-time Built-In Self-Test for Memory (MBIST) and

Logic (LBIST) triggered by hardware

Boot-time Built-In Self-Test for ADC and flash memory

triggered by software

•

Two 12-bit analog-to-digital converters (ADCs)

—

16 input channels

Programmable cross triggering unit (CTU) to

synchronize ADCs conversion with timer and

PWM

—

Replicated safety enhanced watchdog

Replicated junction temperature sensor

Non-maskable interrupt (NMI)

16-region memory protection unit (MPU)

Clock monitoring units (CMU)

•

Sine wave generator (D/A with low pass filter)

On-chip CAN/UART bootstrap loader

Single 3.0 V to 3.6 V voltage supply

•

Ambient temperature range –40 °C to 125 °C

Junction temperature range –40 °C to 150 °C

Power management unit (PMU)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...136

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