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SPC5643LF0MMM1 PDF预览

SPC5643LF0MMM1

更新时间: 2024-10-28 06:13:19
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飞思卡尔 - FREESCALE 微控制器PC
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98页 1601K
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MPC5643L Microcontroller Data Sheet

SPC5643LF0MMM1 数据手册

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Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5643L  
Rev. 3, 10/2009  
MPC5643L  
MPC5643L Microcontroller  
Data Sheet  
LQFP 144  
20 x 20 x 1.4 mm  
257 MAPBGA  
14 x 14 x 1.4 mm  
• GPIOs individually programmable as input, output or  
special function  
• Three 6-channel general-purpose eTimer units  
• Two FlexPWM units  
– Four 16-bit channels per module  
• Communications interfaces  
• High-performance e200z4d dual core  
– 32-bit Power Architecture™ Book E CPU  
– Core frequency as high as 120 MHz  
– Dual issue five-stage pipeline core  
Variable Length Encoding (VLE)  
– Memory Management Unit (MMU)  
– 4 KB instruction cache with error detection code  
– Signal processing engine (SPE)  
– Two LINFlex channels  
– Three DSPI channels with automatic chip select  
generation  
– Two FlexCAN interfaces (2.0B Active) with 32 message  
objects  
• Memory available  
– 1 MB Flash memory with ECC  
– Built-in RWW capabilities for EEPROM emulation  
– As much as 128 KB on-chip RAM with ECC  
• SIL3/ASILD innovative safety concept: LockStep mode  
and Fail-safe protection  
– FlexRay module (V2.1) with dual channel, up to 64  
message objects and speed as fast as 10 Mbit/s  
• Two 12-bit analog-to-digital converters (ADCs)  
– 16 input channels  
– Programmable cross triggering unit (CTU) to  
synchronize ADCs conversion with timer and PWM  
• Sine wave generator (D/A with low pass filter)  
• On-chip CAN/UART/FlexRay Bootstrap loader  
• Single 3.0 V to 3.6 V voltage supply  
• Ambient temperature range –40 °C to 125 °C  
• Junction temperature range –40 °C to 150 °C  
– Sphere of replication (SoR) for key components (such as  
CPU core, DMA, crossbar switch)  
– Fault collection and control unit (FCCU)  
– Redundancy control and checker unit (RCCU) on  
outputs of the SoR connected to FCCU  
– Boot-time Built-In Self-Test for Memory (MBIST) and  
Logic (LBIST) triggered by hardware  
– Boot-time Built-In Self-Test for ADC and flash memory  
triggered by software  
– Replicated safety enhanced watchdog  
– Replicated junction temperature sensor  
– Non-maskable interrupt (NMI)  
– 16-region memory protection unit (MPU)  
– Clock monitoring units (CMU)  
– Power management unit (PMU)  
– Cyclic redundancy check (CRC) unit  
• Decoupled Parallel mode for high performance use of  
replicated cores  
• Nexus Class 3+ interface  
• Interrupts  
– Replicated 16-priority controller  
– Replicated 16-channel eDMA controller  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2009. All rights reserved.  
Preliminary—Subject to Change Without Notice  

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