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SNJ54HC240WR PDF预览

SNJ54HC240WR

更新时间: 2024-11-02 21:17:15
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
22页 1171K
描述
HC/UH SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDFP20, CERAMIC, DFP-20

SNJ54HC240WR 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.35系列:HC/UH
JESD-30 代码:R-GDFP-F20长度:13.72 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):225 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.45 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.92 mm
Base Number Matches:1

SNJ54HC240WR 数据手册

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ꢊ ꢅꢋꢌꢍ ꢎꢏꢐ ꢐ ꢑꢒꢀ ꢌꢁꢓ ꢍ ꢔꢁꢑ ꢓ ꢒꢔ ꢕ ꢑꢒ  
SCLS128D − DECEMBER 1982 − REVISED AUGUST 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
6-mA Output Drive at 5 V  
High-Current Outputs Drive Up To 15  
LSTTL Loads  
Low Input Current of 1 µA Max  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
D
Low Power Consumption, 80-µA Max I  
CC  
D
Typical t = 9 ns  
pd  
SN54HC240 . . . J OR W PACKAGE  
SN74HC240 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HC240 . . . FK PACKAGE  
(TOP VIEW)  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
3
2
1
20 19  
18  
1A2  
2Y3  
1A3  
2Y2  
1A4  
1Y1  
2A4  
1Y2  
2A3  
4
5
6
7
8
17  
16  
15  
14 1Y3  
9 10 11 12 13  
description/ordering information  
These octal buffers and line drivers are designed specifically to improve both the performance and density of  
3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240  
devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HC240N  
SN74HC240N  
SN74HC240DW  
SN74HC240DWR  
SN74HC240NSR  
SN74HC240DBR  
SN74HC240PW  
SN74HC240PWR  
SN74HC240PWT  
SNJ54HC240J  
SOIC − DW  
HC240  
SOP − NS  
HC240  
HC240  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC240  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC240J  
SNJ54HC240W  
SNJ54HC240FK  
SNJ54HC240W  
SNJ54HC240FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢊ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢰꢔ ꢍꢘ ꢙꢒ ꢐ ꢘꢗꢱꢂ ꢗꢂꢈ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢫꢥ ꢞ ꢭꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢪ ꢊ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢫꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢈ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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