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SNJ54F30FKR PDF预览

SNJ54F30FKR

更新时间: 2024-11-24 21:18:19
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
16页 811K
描述
F/FAST SERIES, 8-INPUT NAND GATE, CQCC20, CERAMIC, LCC-20

SNJ54F30FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:CERAMIC, LCC-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.55系列:F/FAST
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:1输入次数:8
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER最大电源电流(ICC):4 mA
传播延迟(tpd):6 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SNJ54F30FKR 数据手册

 浏览型号SNJ54F30FKR的Datasheet PDF文件第2页浏览型号SNJ54F30FKR的Datasheet PDF文件第3页浏览型号SNJ54F30FKR的Datasheet PDF文件第4页浏览型号SNJ54F30FKR的Datasheet PDF文件第5页浏览型号SNJ54F30FKR的Datasheet PDF文件第6页浏览型号SNJ54F30FKR的Datasheet PDF文件第7页 
SN54F30, SN74F30  
8-INPUT POSITIVE-NAND GATES  
SDFS043A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F30 . . . J PACKAGE  
SN74F30 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
A
B
V
CC  
NC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
description  
C
H
These devices contain a single 8-input NAND  
gate. They perform the Boolean functions  
Y = A B C D E F G H or  
Y = A + B + C + D + E + F + G + H in positive logic.  
D
G
E
F
GND  
NC  
NC  
Y
8
The SN54F30 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F30 is characterized for  
operation from 0°C to 70°C.  
SN54F30 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
3
2
1
20 19  
18  
INPUTS  
A–H  
OUTPUT  
Y
C
NC  
D
H
4
5
6
7
8
NC  
G
17  
16  
15  
14  
All inputs H  
L
One or more inputs L  
H
NC  
E
NC  
NC  
9 10 11 12 13  
logic symbol  
1
&
A
2
B
3
NC – No internal connection  
C
4
D
8
5
Y
E
6
F
11  
G
12  
H
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
logic diagram (positive logic)  
1
A
B
C
D
E
F
2
3
4
8
Y
5
6
11  
12  
G
H
Pin numbers shown are for the D, J, and N packages.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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