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SN74LVTH16541DLR PDF预览

SN74LVTH16541DLR

更新时间： 2024-01-08 03:05:18
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
13页 314K
描述
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LVTH16541DLR 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61其他特性：WITH DUAL OUTPUT ENABLE
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G48长度：15.875 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V最大电源电流（ICC）：5 mA
Prop。Delay @ Nom-Sup：3.5 ns传播延迟（tpd）：3.8 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

SN74LVTH16541DLR 数据手册

 浏览型号SN74LVTH16541DLR的Datasheet PDF文件第2页浏览型号SN74LVTH16541DLR的Datasheet PDF文件第3页浏览型号SN74LVTH16541DLR的Datasheet PDF文件第4页浏览型号SN74LVTH16541DLR的Datasheet PDF文件第5页浏览型号SN74LVTH16541DLR的Datasheet PDF文件第6页浏览型号SN74LVTH16541DLR的Datasheet PDF文件第7页 
SN54LVTH16541, SN74LVTH16541  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS691E–MAY 1997–REVISED NOVEMBER 2006  
FEATURES  
SN54LVTH16541 . . . WD PACKAGE  
SN74LVTH16541 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
•
Members of the Texas Instruments Widebus™  
Family  
•
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V Operation  
and Low Static-Power Dissipation  
1OE1  
1Y1  
1OE2  
1A1  
1
2
3
4
5
6
7
8
9
48  
47  
1Y2  
GND  
1Y3  
46 1A2  
•
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
GND  
1A3  
1A4  
45  
44  
43  
42  
3.3-V VCC  
)
1Y4  
•
•
•
•
•
•
•
•
Support Unregulated Battery Operation Down  
to 2.7 V  
V
CC  
V
CC  
1Y5  
1Y6  
GND 10  
1Y7  
1Y8  
2Y1  
41 1A5  
40 1A6  
39 GND  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
Ioff and Power-Up 3-State Support Hot  
Insertion  
1A7  
1A8  
2A1  
11  
12  
13  
38  
37  
36  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
2Y2 14  
GND 15  
2Y3 16  
2Y4 17  
35 2A2  
34 GND  
33 2A3  
32 2A4  
Distributed VCC and GND Pin Configuration  
Minimizes High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
V
CC  
V
CC  
18  
31  
2Y5 19  
2Y6 20  
GND 21  
2Y7 22  
2Y8 23  
2OE1 24  
30 2A5  
29 2A6  
28 GND  
27 2A7  
26 2A8  
25 2OE2  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
•
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package Using  
25-mil Center-to-Center Spacings  
DESCRIPTION/ORDERING INFORMATION  
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the  
capability to provide a TTL interface to a 5-V system environment.  
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable  
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must  
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit  
buffer section are in the high-impedance state.  
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74LVTH16541DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH16541DLG4 TI

完全替代

 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTH16541DL TI

完全替代

 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
74LVTH16541DLRG4 TI

功能相似

 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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