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SN74LVC573A-Q1_15

更新时间： 2024-09-29 02:58:15
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德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 192K
描述
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVC573A-Q1_15 数据手册

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SCAS714A − SEPTEMBER 2003 − REVISED MAY 2004  
D
Qualification in Accordance With  
AEC-Q100  
D
D
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
†
3.3-V V  
)
CC  
D
Qualified for Automotive Applications  
I
Supports Partial-Power-Down Mode  
off  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
Operation  
DW OR PW PACKAGE  
(TOP VIEW)  
D
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
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15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
D
D
D
D
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max t of 6.9 ns at 3.3 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
GND  
†
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V  
operation.  
CC  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − DW  
Reel of 2000  
Reel of 2000  
SN74LVC573AQDWRQ1  
SN74LVC573AQPWRQ1  
L573AQ1  
L573AQ1  
−40°C to 125°C  
TSSOP − PW  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

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