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SN74LVC2952ADGVR PDF预览

SN74LVC2952ADGVR

更新时间： 2024-02-06 19:30:34
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德州仪器 - TI 总线收发器输出元件
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14页 287K
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OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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SN74LVC2952ADGVR 数据手册

 浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第2页浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第3页浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第4页浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第5页浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第6页浏览型号SN74LVC2952ADGVR的Datasheet PDF文件第7页 
SN74LVC2952A  
OCTAL BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS311I–JANUARY 1993–REVISED MARCH 2005  
FEATURES  
DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 8.2 ns at 3.3 V  
B8  
B7  
B6  
B5  
B4  
V
CC  
1
2
3
4
5
6
7
8
9
10  
24  
23 A8  
22 A7  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
A6  
A5  
21  
20  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
B3  
B2  
B1  
19 A4  
18 A3  
17 A2  
16 A1  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
OEAB  
CLKAB  
15  
OEBA  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
CLKENAB 11  
GND 12  
14 CLKBA  
13 CLKENBA  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions  
between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of  
the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking  
the output-enable (OEAB or OEBA) input low accesses the data on either port.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC2952ADW  
TOP-SIDE MARKING  
LVC2952A  
Tube of 25  
SOIC – DW  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 60  
SN74LVC2952ADWR  
SN74LVC2952ANSR  
SN74LVC2952ADBR  
SN74LVC2952APW  
SOP – NS  
LVC2952A  
LE952A  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
Reel of 2000  
Reel of 250  
SN74LVC2952APWR  
SN74LVC2952APWT  
LE952A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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