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SN74LVC2G00DCT PDF预览

SN74LVC2G00DCT

更新时间: 2024-11-04 13:02:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
13页 526K
描述
LVC/LCX/Z SERIES, DUAL 2-INPUT NAND GATE, PDSO8, PLASTIC, TSSOP-8

SN74LVC2G00DCT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, TSSOP-8针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.33Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G8
长度:2.95 mm逻辑集成电路类型:NAND GATE
功能数量:2输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH传播延迟(tpd):8.6 ns
认证状态:Not Qualified座面最大高度:1.3 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:2.8 mm
Base Number Matches:1

SN74LVC2G00DCT 数据手册

 浏览型号SN74LVC2G00DCT的Datasheet PDF文件第2页浏览型号SN74LVC2G00DCT的Datasheet PDF文件第3页浏览型号SN74LVC2G00DCT的Datasheet PDF文件第4页浏览型号SN74LVC2G00DCT的Datasheet PDF文件第5页浏览型号SN74LVC2G00DCT的Datasheet PDF文件第6页浏览型号SN74LVC2G00DCT的Datasheet PDF文件第7页 
SN74LVC2G00  
DUAL 2-INPUT POSITIVE-NAND GATE  
www.ti.com  
SCES193LAPRIL 1999REVISED JANUARY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Supports 5-V VCC Operation  
Ioff Supports Partial-Power-Down Mode  
Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.3 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
2B  
VCC  
1Y  
2B  
2A  
1
2
3
4
8
7
6
5
1A  
1B  
VCC  
1Y  
2B  
2A  
1
2
3
4
8
7
6
5
1A  
1B  
3 6  
2 7  
1 8  
1B  
1Y  
2Y  
VCC  
1A  
GND  
2Y  
GND  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC2G00 performs the Boolean function Y = A B or Y = A + B in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SSOP – DCT  
Reel of 3000  
SN74LVC2G00YZPR  
_ _ _CA_  
C00_ _ _  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC2G00DCTR  
SN74LVC2G00DCUR  
SN74LVC2G00DCUT  
–40°C to 85°C  
VSSOP – DCU  
C00_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74LVC2G00DCT 替代型号

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