SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416J–DECEMBER 2002–REVISED JANUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
•
•
•
•
•
Supports 5-V VCC Operation
ESD Protection Exceeds JESD 22
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
•
Choose From Nine Specific Logic Functions
Ioff Supports Partial-Power-Down Mode
Operation
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
3
4
Y
V
In0
GND
In1
1
2
3
6
5
4
In1
GND
In0
In2
In1
GND
In0
In2
1
2
3
6
5
4
1
2
3
6
In1
GND
In0
In2
V
2 5
CC
V
Y
CC
V
Y
CC
1
6
In2
5
4
CC
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Reel of 3000
SN74LVC1G97YZPR
_ _ _CS_
Reel of 3000
Reel of 3000
Reel of 4000
SN74LVC1G97DBVR
SN74LVC1G97DCKR
SN74LVC1G97DRLR
C97_
CS_
CS_
–40°C to 85°C
SOT (SC-70) – DCK
SOT (SOT-563) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.