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SN74LV4320AZKFR PDF预览

SN74LV4320AZKFR

更新时间: 2024-09-14 21:53:35
品牌 Logo 应用领域
德州仪器 - TI 双倍数据速率
页数 文件大小 规格书
23页 476K
描述
LOW-POWER, DUAL-SUPPLY, LEVEL-TRANSLATING COMPACTFLASH INTERFACE WITH 16-BIT DATA, 11-BIT ADDRESS, AND 13-BIT CONTROL LINES

SN74LV4320AZKFR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:BGA
包装说明:LFBGA, BGA114,6X19,32针数:114
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:7.06接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PBGA-B114JESD-609代码:e1
长度:16 mm湿度敏感等级:3
功能数量:1端子数量:114
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA114,6X19,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8/5,3.3/5 V认证状态:Not Qualified
座面最大高度:1.4 mm子类别:Other Interface ICs
最大压摆率:0.01 mA最大供电电压:5.5 V
最小供电电压:1.65 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.5 mm
Base Number Matches:1

SN74LV4320AZKFR 数据手册

 浏览型号SN74LV4320AZKFR的Datasheet PDF文件第2页浏览型号SN74LV4320AZKFR的Datasheet PDF文件第3页浏览型号SN74LV4320AZKFR的Datasheet PDF文件第4页浏览型号SN74LV4320AZKFR的Datasheet PDF文件第5页浏览型号SN74LV4320AZKFR的Datasheet PDF文件第6页浏览型号SN74LV4320AZKFR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ ꢇꢈ ꢉ  
ꢄ ꢊꢋꢌꢍ ꢊꢋ ꢎ ꢏꢐ ꢑꢒ ꢉꢄ ꢌꢀꢒ ꢍꢍꢄꢓꢐ ꢄ ꢎꢅꢎ ꢄꢌ ꢔꢏꢉꢁ ꢀꢄ ꢉꢔ ꢕꢁꢖ ꢗꢘ ꢙꢚ ꢛ ꢜ ꢝꢞ ꢟꢛ ꢠ ꢡ ꢕꢁꢔ ꢎꢏ ꢞꢉ ꢗꢎ  
ꢋ ꢕ ꢔꢢ ꢣ ꢤ ꢌꢥꢕ ꢔ ꢑꢉꢔꢉꢐ ꢣꢣ ꢌꢥꢕ ꢔ ꢉꢑꢑ ꢏꢎꢀꢀ ꢐ ꢉꢁꢑ ꢣ ꢆ ꢌꢥꢕ ꢔ ꢗꢊ ꢁꢔ ꢏꢊ ꢄ ꢄꢕ ꢁ ꢎꢀ  
SCES628A − APRIL 2005 − REVISED APRIL 2005  
D
D
D
D
Member of the Texas Instruments  
Widebus+Family  
Designed to Optimize Power Savings in  
Portable Applications  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1.65-V to 5.5-V Level Translation Using Dual  
Supplies  
ESD  
− 15-kV Human-Body Model  
+ 4-kV IEC61000-4-2, Contact Discharge  
(Latch-Up Immune)  
Matched Pinout With CompactFlash(CF)  
Connector Pin Configurations to Optimize  
PCB Layout  
D
Input-Disable Feature Allows Floating Input  
Conditions  
description/ordering information  
This CompactFlash(CF) interface chip is designed to provide a single-chip solution for CF card interfaces.  
Separate V rails for the system bus side and the CF connector bus side allow voltage-level shifting. This is  
CC  
helpful for interfacing between a core chipset, which may operate from 3.3 V down to 1.65 V, and CF cards, which  
operate from 3.3-V or 5-V supply voltages. All the input buffers feature the input-disable function, which allows  
conditional floating input signals. The input, output, and I/O buffers on the CF connector side have been defined  
to comply with CF+ and CompactFlash specification revisions 1.4 and 2.0.  
This device has 16-bit data lines and 24-bit address/command lines. CD1 and CD2 have internal pullup resistors  
to pull them to a high logic state if there is no card in the CF slot. The presence of a CF card in the CF card slot  
generates a low logic signal at SCD. A separate power-supply pin, V  
, controls the SCD output buffer. The  
CC_SD  
SCD signal can be used to control a voltage regulator, which may power the CF slot and the CF side of this  
device. V is particularly helpful when the core processor operates at a low V , but the regulator needs  
CC_SD  
CC  
a higher control signal voltage.  
The MASTER_EN signal controls all the buffers and transceivers except CD1 and CD2. If MASTER_EN is high,  
the SN74LV4320A is in a power-down mode. The BUF_EN signal, in conjunction with MASTER_EN, controls  
the 11-bit address lines and 13-bit control/command lines.  
The 16-bit data lines use two separate enable signals. ENL, in conjunction with MASTER_EN, controls the lower  
8-bit data lines (D07−D00). ENH, in conjunction with MASTER_EN, controls the upper 8-bit data lines  
(D15−D08). A DIR(S/CF) input controls the data direction between the system bus and the CF card. An  
additional DIR_OUT pin generates the DIR(S/CF) signal using the SOE and SIORD signals. With either SOE  
or SIORD being low, the data direction is from the CF card side to the system side (DIR_OUT = L). DIR(S/CF)  
and DIR_OUT are placed adjacent to each other, which is convenient for connecting DIR(S/CF) and DIR_OUT,  
if DIR_OUT is used. This saves an additional signal from the system controller to control the data direction.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C  
LFBGA − GKF Tape and reel  
SN74LV4320AGKFR  
LM320A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
CompactFlash is a trademark of Sandisk Corporation.  
ꢔꢫ  
Copyright 2005, Texas Instruments Incorporated  
ꢝ ꢫ ꢠ ꢝꢦ ꢧꢲ ꢘꢨ ꢛ ꢟꢟ ꢚꢛ ꢩ ꢛ ꢙ ꢫ ꢝ ꢫ ꢩ ꢠ ꢮ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LV4320AZKFR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV4320AGKFR TI

完全替代

LOW-POWER, DUAL-SUPPLY, LEVEL-TRANSLATING COMPACTFLASH INTERFACE WITH 16-BIT DATA, 11-BIT

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