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SN74LV240ADBE4 PDF预览

SN74LV240ADBE4

更新时间： 2024-11-05 15:52:19
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 130K
描述
LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20

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SN74LV240ADBE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：SSOP,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.44系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：7.2 mm逻辑集成电路类型：BUS DRIVER
湿度敏感等级：1位数：4
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：17 ns认证状态：Not Qualified
座面最大高度：2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

SN74LV240ADBE4 数据手册

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SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV240 . . . J OR W PACKAGE  
SN74LV240 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Typical V  
(Output V  
Undershoot)  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
OHV  
OH  
> 2 V at V , T = 25°C  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
13 2A2  
12 1Y4  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
11  
2A1  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV240 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
These octal buffers/drivers are designed for 2.7-V  
to 5.5-V V operation.  
17  
16  
15  
14  
CC  
The ’LV240 are designed specifically to improve  
both the performance and density of 3-state  
memory address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
9 10 11 12 13  
The ’LV240 are organized as two 4-bit buffers/line  
drivers with separate output-enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
The SN74LV240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV240 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV240 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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