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SN74LV240DB PDF预览

SN74LV240DB

更新时间： 2024-11-24 23:03:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 137K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LV240DB 技术参数

生命周期：Obsolete包装说明：SSOP,
Reach Compliance Code：unknown风险等级：5.72
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G20
长度：7.2 mm逻辑集成电路类型：BUS DRIVER
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
传播延迟（tpd）：18 ns认证状态：Not Qualified
座面最大高度：2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：5.3 mmBase Number Matches：1

SN74LV240DB 数据手册

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SN54LV240, SN74LV240  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS193B – FEBRUARY 1993 – REVISED APRIL 1996  
SN54LV240 . . . J OR W PACKAGE  
SN74LV240 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
OHV  
CC  
OH  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
13 2A2  
12 1Y4  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
11  
2A1  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV240 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
These octal buffers/drivers are designed for 2.7-V  
to 5.5-V V operation.  
17  
16  
15  
14  
CC  
The ’LV240 are designed specifically to improve  
both the performance and density of 3-state  
memory address drivers, clock drivers, and  
bus-oriented receivers and transmitters.  
9 10 11 12 13  
The ’LV240 are organized as two 4-bit buffers/line  
drivers with separate output-enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
The SN74LV240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV240 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV240 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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