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SN74LV240ADWE4 PDF预览

SN74LV240ADWE4

更新时间： 2024-01-19 10:41:35
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
15页 355K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LV240ADWE4 数据手册

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SCLS384H − SEPTEMBER 1997 − REVISED APRIL 2005  
SN54LV240A . . . J OR W PACKAGE  
SN74LV240A . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
2-V to 5.5-V V  
Operation  
CC  
Max t of 6.5 ns at 5 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
= 3.3 V, T = 25°C  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
A
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
13 2A2  
12 1Y4  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
11  
2A1  
− 1000-V Charged-Device Model (C101)  
SN54LV240A . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These octal buffers/drivers are designed for 2-V to  
5.5-V V  
operation.  
CC  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
The ’LV240A devices are designed specifically to  
improve both the performance and density of  
3-state memory address drivers, clock drivers,  
and bus-oriented receivers and transmitters.  
17  
16  
15  
14  
9 10 11 12 13  
These devices are organized as two 4-bit  
buffers/line drivers with separate output-enable  
(OE) inputs. When OE is low, the device passes  
data from the A inputs to the Y outputs. When OE  
is high, the outputs are in the high-impedance  
state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 20  
Tube of 85  
Tube of 55  
SN74LV240ADW  
SN74LV240ADWR  
SN74LV240ANSR  
SN74LV240ADBR  
SN74LV240APW  
SN74LV240APWR  
SN74LV240APWT  
SOIC − DW  
LV240A  
SOP − NS  
74LV240A  
LV240A  
SSOP − DB  
−40°C to 85°C  
TSSOP − PW  
LV240A  
TVSOP − DGV  
CDIP − J  
SN74LV240ADGVR  
SNJ54LV240AJ  
LV240A  
SNJ54LV240AJ  
SNJ54LV240AW  
SNJ54LV240AFK  
−55°C to 125°C  
CFP − W  
SNJ54LV240AW  
SNJ54LV240AFK  
LCCC − FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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SN74LV240ADWE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV240ADWRG4 TI

完全替代

 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LV240ADWRE4 TI

完全替代

 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LV240ADW TI

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 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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