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SN74LV221A-Q1

更新时间: 2024-02-22 07:23:15
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描述
DUAL MONOSTABLE MULTIVIBRATOR WITH SCHMITT-TRIGGER INPUTS

SN74LV221A-Q1 数据手册

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SN74LV221A-Q1  
www.ti.com  
SCLS692A OCTOBER 2005REVISED APRIL 2008  
DUAL MONOSTABLE MULTIVIBRATOR  
WITH SCHMITT-TRIGGER INPUTS  
Check for Samples: SN74LV221A-Q1  
1
FEATURES  
Qualified for Automotive Applications  
2-V to 5.5-V VCC Operation  
Supports Mixed-Mode Voltage Operation on  
All Ports  
Schmitt-Trigger Circuitry on A, B, and CLR  
Inputs for Slow Transition Rates  
Overriding Clear Terminates Output Pulse  
Glitch-Free Power-Up Reset on Outputs  
Ioff Supports Partial-Power-Down Mode  
Operation  
PW PACKAGE  
(TOP VIEW)  
1A  
1B  
VCC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
1Rext/Cext  
1Cext  
1Q  
1CLR  
1Q  
2Q  
12 2Q  
11  
10  
9
2Cext  
2Rext/Cext  
GND  
2CLR  
2B  
2A  
DESCRIPTION/ORDERING INFORMATION  
The SN74LV221A is a dual multivibrator designed for 2-V to 5.5-V VCC operation. Each multivibrator has a  
negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as  
an inhibit input.  
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the  
A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In  
the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.  
The output pulse duration is programmable by selecting external resistance and capacitance values. The  
external timing capacitor must be connected between Cext and Rext/Cext(positive) and an external resistor  
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor  
between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.  
Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input  
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition  
rates with jitter-free triggering at the outputs.  
Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of the  
timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any  
duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing  
components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering  
and clearing sequences are illustrated in the input/output timing diagram.  
The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing  
components. An example of this distribution for the SN74LV221A-Q1 is shown in Figure 8. Variations in output  
pulse duration versus supply voltage and temperature are shown in Figure 5.  
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,  
without applying a reset pulse.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the devices when they are powered down.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 20052008, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74LV221A-Q1 替代型号

型号 品牌 替代类型 描述 数据表
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