Datasheet > SN74LS90J

SN74LS90J

更新时间： 2024-09-15 07:58:59

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	166K
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SN74LS90J

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SN74LS90J 数据手册

SN74LS90

DECADE COUNTER;

DIVIDE-BY-TWELVE

COUNTER;

4-BIT BINARY COUNTER

http://onsemi.com

The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are

high-speed 4-bit ripple type counters partitioned into two sections.

Each counter has a divide-by-two section and either a divide-by-five

(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which

are triggered by a HIGH-to-LOW transition on the clock inputs. Each

section can be used separately or tied together (Q to CP) to form BCD,

bi-quinary, modulo-12, or modulo-16 counters. All of the counters

have a 2-input gated Master Reset (Clear), and the LS90 also has a

2-input gated Master Set (Preset 9).

DECADE COUNTER;

DIVIDE-BY-TWELVE COUNTER;

4-BIT BINARY COUNTER

LOW POWER SCHOTTKY

• Low Power Consumption . . . Typically 45 mW

• High Count Rates . . . Typically 42 MHz

J SUFFIX

CERAMIC

CASE 632-08

• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,

Binary

• Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES

LOADING (Note a)

HIGH

LOW

N SUFFIX

PLASTIC

CASE 646-06

Clock (Active LOW going edge) Input to

÷2 Section

Clock (Active LOW going edge) Input to

÷5 Section (LS90), ÷6 Section (LS92)

0.5 U.L.

1.5 U.L.

0.5 U.L.

2.0 U.L.

1.0 U.L.

Clock (Active LOW going edge) Input to

÷8 Section (LS93)

MR , MR

Master Reset (Clear) Inputs

0.5 U.L.

10 U.L.

0.25 U.L.

5 (2.5) U.L.

D SUFFIX

SOIC

CASE 751A-02

MS , MS

Master Set (Preset-9, LS90) Inputs

Output from ÷2 Section (Notes b & c)

Outputs from ÷5 (LS90), ÷6 (LS92),

÷8 (LS93) Sections (Note b)

Q , Q , Q

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

ORDERING INFORMATION

b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)

b. Temperature Ranges.

SN54LSXXJ

SN74LSXXN

SN74LSXXD

Ceramic

Plastic

SOIC

c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.

d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.

LOGIC SYMBOL

LS92

1 2

LS90

LS93

Q Q Q Q

0 1 2 3

Q Q Q

0 1 2 3

1 2

2 3 12 9

V = PIN 5

8 11

2 3 12

8 11

6 7 12 11

= PIN 5

GND = PIN 10

NC = PIN 4, 6, 7, 13

NC = PINS 4, 13

NC = PINS 2, 3, 4, 13

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

SN74LS90/D

July, 2006 − Rev. 6

12 3 4 5 6 7

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与SN74LS90J相关器件

型号	品牌	获取价格	描述	数据表
SN74LS90JD	ETC	获取价格	Asynchronous Up Counter
SN74LS90JP4	TI	获取价格	IC,COUNTER,UP,DECADE,LS-TTL,DIP,14PIN,CERAMIC
SN74LS90N	TI	获取价格	DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SN74LS90N	MOTOROLA	获取价格	DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
SN74LS90N	ONSEMI	获取价格	DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
SN74LS90N1	TI	获取价格	IC,COUNTER,UP,DECADE,LS-TTL,DIP,14PIN,PLASTIC
SN74LS90N3	ROCHESTER	获取价格	Decade Counter,
SN74LS90N8	ROCHESTER	获取价格	Decade Counter, LS Series, Asynchronous, Negative Edge Triggered, 3-Bit, Up Direction, TTL
SN74LS90NDS	ETC	获取价格	Asynchronous Up Counter
SN74LS90NE4	TI	获取价格	DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS

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