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SN74LS273JD PDF预览

SN74LS273JD

更新时间: 2024-11-04 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器逻辑集成电路光电二极管
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5页 187K
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SN74LS273JD 数据手册

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SN54/74LS273  
OCTAL D FLIP-FLOP WITH CLEAR  
The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of  
eight D-Type Flip-Flops with a Common Clock and an asynchronous active  
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3  
inch lead spacing.  
8-Bit High Speed Register  
Parallel Register  
OCTAL D FLIP-FLOP  
WITH CLEAR  
Common Clock and Master Reset  
Input Clamp Diodes Limit High-Speed Termination Effects  
LOW POWER SCHOTTKY  
CONNECTION DIAGRAM DIP (TOP VIEW)  
J SUFFIX  
CERAMIC  
CASE 732-03  
20  
1
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
PIN NAMES  
LOADING (Note a)  
1
HIGH  
LOW  
CP  
Clock (Active HIGH Going Edge) Input  
Data Inputs  
Master Reset (Active LOW) Input  
Register Outputs (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
DW SUFFIX  
SOIC  
CASE 751D-03  
D D  
0
7
MR  
Q Q  
0
20  
5 (2.5) U.L.  
7
1
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial  
(74) Temperature Ranges.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
TRUTH TABLE  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
MR CP  
D
Q
x
x
L
H
H
X
X
H
L
L
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
X = Immaterial  
LOGIC DIAGRAM  
FAST AND LS TTL DATA  
5-447  

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