SN74LS273W

更新时间： 2024-11-03 23:06:19

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
6页	98K
描述
OCTAL D-TYPE FLIP-FLOP WITH CLEAR

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数据手册

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SN74LS273W 数据手册

SN54273, SN54LS273, SN74273, SN74LS273

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

SDLS090 – OCTOBER 1976 – REVISED MARCH 1988

SN54273, SN74LS273 . . . J OR W PACKAGE

SN74273 . . . N PACKAGE

• Contains Eight Flip-Flops With Single-Rail

Outputs

SN74LS273 . . . DW OR N PACKAGE

(TOP VIEW)

• Buffered Clock and Direct Clear Inputs

• Individual Data Input to Each Flip-Flop

• Applications Include:

Buffer/Storage Registers

Shift Registers

CLR

Pattern Generators

16 7Q

15 6Q

description

CLK

These monolithic, positive-edge-triggered flip-

flops utilize TTL circuitry to implement D-type

flip-flop logic with a direct clear input.

GND

Information at the D inputs meeting the setup time

requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a particular voltage level and

is not directly related to the transition time of the

positive-going pulse. When the clock input is at

either the high or low level, the D input signal has

no effect ar the output.

SN54LS273 . . . FK PACKAGE

(TOP VIEW)

20 19

These flip-flops are guaranteed to respond to

clock frequencies ranging form 0 to 30 megahertz

while maximum clock frequency is typically 40

megahertz. Typical power dissipation is 39

milliwatts per flip-flop for the ′273 and 10 milliwatts

for the ′LS273.

9 10 11 12 13

†

FUNCTION TABLE

(each flip-flop)

logic symbol

INPUTS

CLR

OUTPUT

CLEAR CLOCK

CLK

↑

†

This symbol is in accordance with ANSI/IEEE Std.

91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, J, N, and W packages.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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