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SN74LS273DWRG4 PDF预览

SN74LS273DWRG4

更新时间: 2024-11-04 21:03:27
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 419K
描述
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, PLASTIC, SO-20

SN74LS273DWRG4 技术参数

生命周期:Contact Manufacturer包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57系列:LS
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):27 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:30 MHzBase Number Matches:1

SN74LS273DWRG4 数据手册

 浏览型号SN74LS273DWRG4的Datasheet PDF文件第2页浏览型号SN74LS273DWRG4的Datasheet PDF文件第3页浏览型号SN74LS273DWRG4的Datasheet PDF文件第4页浏览型号SN74LS273DWRG4的Datasheet PDF文件第5页浏览型号SN74LS273DWRG4的Datasheet PDF文件第6页浏览型号SN74LS273DWRG4的Datasheet PDF文件第7页 
SN54273, SN54LS273, SN74273, SN74LS273  
OCTAL D-TYPE FLIP-FLOP WITH CLEAR  
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988  
SN54273, SN74LS273 . . . J OR W PACKAGE  
SN74273 . . . N PACKAGE  
Contains Eight Flip-Flops With Single-Rail  
Outputs  
SN74LS273 . . . DW OR N PACKAGE  
(TOP VIEW)  
Buffered Clock and Direct Clear Inputs  
Individual Data Input to Each Flip-Flop  
Applications Include:  
Buffer/Storage Registers  
Shift Registers  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
8Q  
8D  
7D  
Pattern Generators  
16 7Q  
15 6Q  
description  
14  
13  
12  
11  
6D  
5D  
5Q  
CLK  
These monolithic, positive-edge-triggered flip-  
flops utilize TTL circuitry to implement D-type  
flip-flop logic with a direct clear input.  
GND  
Information at the D inputs meeting the setup time  
requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a particular voltage level and  
is not directly related to the transition time of the  
positive-going pulse. When the clock input is at  
either the high or low level, the D input signal has  
no effect ar the output.  
SN54LS273 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
These flip-flops are guaranteed to respond to  
clock frequencies ranging form 0 to 30 megahertz  
while maximum clock frequency is typically 40  
megahertz. Typical power dissipation is 39  
milliwatts per flip-flop for the 273 and 10 milliwatts  
for the LS273.  
17  
16  
15  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each flip-flop)  
logic symbol  
INPUTS  
1
CLR  
OUTPUT  
Q
EN  
C1  
CLEAR CLOCK  
D
X
H
L
11  
CLK  
L
H
H
H
X
L
H
L
3
1D  
4
2
5
6
1D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
2D  
7
L
X
Q
0
3D  
8
9
4D  
13  
5D  
14  
6D  
17  
7D  
18  
8D  
12  
15  
16  
19  
This symbol is in accordance with ANSI/IEEE Std.  
91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the DW, J, N, and W packages.  
Copyright 1988, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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