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SN74LS195AND PDF预览

SN74LS195AND

更新时间: 2024-11-12 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
6页 223K
描述
LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, 648-05

SN74LS195AND 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.28
其他特性:COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT计数方向:RIGHT
系列:LSJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:20.07 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:30000000 Hz
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):26 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:39 MHzBase Number Matches:1

SN74LS195AND 数据手册

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SN54/74LS195A  
UNIVERSAL 4-BIT  
SHIFT REGISTER  
The SN54/74LS195A is a high speed 4-Bit Shift Register offering typical  
shift frequencies of 39 MHz. It is useful for a wide variety of register and  
counting applications. It utilizes the Schottky diode clamped process to  
achieve high speeds and is fully compatible with all Motorola TTL products.  
UNIVERSAL 4-BIT  
SHIFT REGISTER  
Typical Shift Right Frequency of 39 MHz  
Asynchronous Master Reset  
LOW POWER SCHOTTKY  
J, K Inputs to First Stage  
Fully Synchronous Serial or Parallel Data Transfers  
Input Clamp Diodes Limit High Speed Termination Effects  
J SUFFIX  
CERAMIC  
CASE 620-09  
CONNECTION DIAGRAM DIP (TOP VIEW)  
16  
1
NOTE:  
N SUFFIX  
PLASTIC  
CASE 648-08  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
ORDERING INFORMATION  
PE  
Parallel Enable (Active LOW) Input  
Parallel Data Inputs  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
P
0
J
– P  
3
SN54LSXXXJ  
Ceramic  
First Stage J (Active HIGH) Input  
First Stage K (Active LOW) Input  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
Parallel Outputs (Note b)  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
K
CP  
MR  
Q
Q
– Q  
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
0
3
3
LOGIC SYMBOL  
Complementary Last Stage Output (Note b)  
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
FAST AND LS TTL DATA  
5-366  

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