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SN74LS196JDS PDF预览

SN74LS196JDS

更新时间： 2024-11-12 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
6页 93K
描述
Decade Counter, LS Series, Asynchronous, Negative Edge Triggered, 3-Bit, Up Direction, TTL, CDIP14, CERAMIC, DIP-14

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SN74LS196JDS 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.54
Is Samacsys：N计数方向：UP
系列：LSJESD-30 代码：R-GDIP-T14
JESD-609代码：e0长度：19.495 mm
负载/预设输入：YES逻辑集成电路类型：DECADE COUNTER
工作模式：ASYNCHRONOUS位数：3
功能数量：2端子数量：14
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V传播延迟（tpd）：62 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Counters最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：7.62 mm
最小 fmax：30 MHzBase Number Matches：1

SN74LS196JDS 数据手册

 浏览型号SN74LS196JDS的Datasheet PDF文件第2页浏览型号SN74LS196JDS的Datasheet PDF文件第3页浏览型号SN74LS196JDS的Datasheet PDF文件第4页浏览型号SN74LS196JDS的Datasheet PDF文件第5页浏览型号SN74LS196JDS的Datasheet PDF文件第6页 
SN54/74LS196  
SN54/74LS197  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddi-  
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)  
sequence or in a bi-quinary mode producing a 50% duty cycle output. The  
SN54/74LS197 contains divide-by-two and divide-by-eight sections which  
can be combined to form a modulo-16 binary counter. Low Power Schottky  
technology is used to achieve typical count rates of 70 MHz and power dis-  
sipation of only 80 mW.  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
LOW POWER SCHOTTKY  
Both circuit types have a Master Reset (MR) input which overrides all other  
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)  
overrides clocked operations and asynchronously loads the data on the Par-  
allel Data inputs (P ) into the flip-flops. This preset feature makes the circuits  
n
J SUFFIX  
CERAMIC  
CASE 632-08  
usable as programmable counters. The circuits can also be used as 4-bit  
latches, loading data from the Parallel Data inputs when PL is LOW and stor-  
ing the data when PL is HIGH.  
14  
1
• Low Power Consumption — Typically 80 mW  
• High Counting Rates — Typically 70 MHz  
• Choice of Counting Modes — BCD, Bi-Quinary, Binary  
• Asynchronous Presettable  
• Asynchronous Master Reset  
• Easy Multistage Cascading  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
• Input Clamp Diodes Limit High Speed Termination Effects  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
MR  
13  
Q
P
P
Q
CP  
D SUFFIX  
SOIC  
CASE 751A-02  
CC  
3
3
1
1
0
14  
12  
11  
10  
9
8
14  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
1
2
3
4
5
6
7
PL  
Q
P
P
Q
CP  
1
GND  
2
2
0
0
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
1.5 U.L.  
1
4
10 3 11  
CP  
Clock (Active LOW Going Edge)  
Input to Divide-by-Two Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Five Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Eight Section  
Master Reset (Active LOW) Input  
Parallel Load (Active LOW) Input  
Data Inputs  
1.0 U.L.  
0
PL  
P
P P P  
0 1 2 3  
8
6
CP  
CP  
0
CP (LS196)  
1
2.0 U.L.  
1.0 U.L.  
1.75 U.L.  
0.8 U.L.  
1
MR  
Q
Q Q Q  
0 1 2 3  
CP (LS197)  
1
MR  
PL  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
13  
V
5
9
2 12  
= PIN 14  
CC  
P –P  
0
0.25 U.L.  
3
GND = PIN 7  
Q –Q  
Outputs (Notes b, c)  
5 (2.5) U.L.  
0
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
c. In addition to loading shown, Q can also drive CP .  
0
1
FAST AND LS TTL DATA  
5-1  
123456

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